ICS2059-02
Clock Multiplier and Jitter Attenuator
output clock will change to reflect the phase of the
newly selected input at a controlled phase slope (rate
of phase change) as influenced by the PLL loop
characteristics.
Functional Description
The ICS2059-02 is a clock generator IC that generates
an output clock directly from an internal VCXO circuit
which works in conjunction with an external quartz
crystal. The VCXO is controlled by an internal PLL
(Phase-Locked Loop) circuit, enabling the device to
perform clock regeneration from an input reference
clock. The ICS2059-02 is configured to provide an
output clock that is the same frequency as the input
clock. There are 12 selectable input / output frequency
ranges, each of which is a submultiple of the supported
quartz crystal frequency range. Please refer to the
Output Clock Selection Table on Page 2.
Quartz Crystal
It is important that the correct type of quartz crystal is
used with the ICS2059-02. Failure to do so may result
in reduced frequency pullability range, inability of the
loop to lock, or excessive output phase jitter.
The ICS2059-02 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input.
The VCXO consists of the external crystal and the
integrated VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the PCB
Layout Recommendations section must be followed.
Most typical PLL clock devices use an internal VCO
(Voltage Controlled Oscillator) for output clock
generation. By using a VCXO with an external crystal,
the ICS2059-02 is able to generate a low jitter, low
phase-noise output clock within a low bandwidth PLL.
This serves to provide input clock jitter attenuation and
enables stable operation with a low-frequency
reference clock.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the external load
capacitance. The ICS2059-02 incorporates variable
load capacitors on-chip which “pull”, or change, the
frequency of the crystal. The crystals specified for use
with the ICS2059-02 are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14 pF. To achieve this, the layout should
use short traces between the ICS2059-02 and the
crystal.
The VCXO circuit requires an external pullable crystal
for operation. External loop filter components enable a
PLL configuration with low loop bandwidth.
Application Information
A complete description of the recommended crystal
parameters is in application note MAN05.
Input / Output Frequency Configuration
The ICS2059-02 is configured to generate an output
frequency that is equal to the input reference
A list of approved crystals is located on the ICST web
site (www.icst.com).
frequency. Clock frequencies that are supported are
those which fall into the ranges listed in the Output
Clock Selection Table on Page 2. Input bits SEL2:0 are
set according to this table, as is the external crystal
frequency. Other input/output frequency combinations
can be used if the necessary integer multiplication
factor “N” appears in the Output Frequency Select
table. fro example, 20 MHz can be generated from
156.25 kHz by using select M0, as N=128.
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish
operating stability. The ICS2059-02 uses external loop
filter components for the following reasons:
1) Larger loop filter capacitor values can be used,
allowing a lower loop bandwidth. This enables the use
of lower input clock reference frequencies and also
input clock jitter attenuation capabilities. Larger loop
filter capacitors also allow higher loop damping factors
when less passband peaking is desired.
Input Mux
The Input Mux serves to select between two alternate
input reference clocks. Upon reselection of the input
clock, clock glitches on the output clock will not be
generated due to the “fly-wheel” effect of the VCXO
(the quartz crystal is a high-Q tuned circuit). When the
input clocks are not phase aligned, the phase of the
2) The loop filter values can be user selected to
optimize loop response characteristics for a given
application.
MDS 2059-02 C
3
Revision 031605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
