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ICS1572M-101 参数 Datasheet PDF下载

ICS1572M-101图片预览
型号: ICS1572M-101
PDF下载: 下载PDF文件 查看货源
内容描述: 用户可编程差分输出图形时钟发生器 [User Programmable Differential Output Graphics Clock Generator]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 19 页 / 279 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS1572  
Phase Detector Gain: For most graphics applications and  
divider ranges, set P[1,0] = 10 and set P[2] = 1. Under  
some circumstances, setting the P[2] bit “on” can reduce  
jitter. During 1572 operation at exact multiples of the  
crystal frequency, P[2] bit = 0 may provide the best jitter  
performance.  
Power-On Initialization  
The ICS1572 has an internal power-on reset circuit that per-  
forms the following functions:  
1) Sets the multiplexer to pass the reference frequency  
to the CLK+ and CLK- outputs.  
2) Selects the modulus of the N1 divider (for the  
LOAD clock) to be four.  
Board Test Support  
It is often desirable to statically control the levels of the output  
pins for circuit board test. The ICS1572 supports this through  
a register programmable mode, AUXEN. When this mode is  
set, two register bits directly control the logic levels of the  
CLK+/CLK- pins and the LOAD pin. This mode is activated  
when the S[0] and S[1] bits are both set to logic 1. See Register  
Mapping for details.  
These functions should allow initialization of most graphics  
systems that cannot immediately provide for register program-  
ming upon system power-up.  
Because the power-on reset circuit is on the VDD supply, and  
because that supply is filtered, care must be taken to allow the  
reset to de-assert before programming. A safe guideline is to  
allow 20 microseconds after the VDD supply reaches 4 volts.  
Power Supplies and Decoupling  
Programming Notes  
The ICS1572has twoVSS pinstoreduce theeffectsofpackage  
inductance. Both pins are connected to the same potential on  
the die (the ground bus). BOTH of these pins should connect  
to the ground plane of the video board as close to the package  
as is possible.  
VCO Frequency Range: Use the post-divider to keep the  
VCO frequency as high as possible within its operating  
range.  
Divider Range: For best results in normal situations (i.e.,  
pixel clock generation for hi-res displays), keep the refer-  
ence divider modulus as short as possible (for a frequency  
at the output of the reference divider in the few hundred  
kHz to several MHz range). If you need to go to a lower  
phase comparator reference frequency (usually required  
for increased frequency accuracy), that is acceptable, but  
jitter performance will suffer somewhat.  
The ICS1572 has a VDDO pin which is the supply of +5 volt  
power to all output drivers. This pin should be connected to the  
power plane (or bus) using standard high-frequency decou-  
plingpractice. That is, capacitors should have lowseries induc-  
tance and be mounted close to the ICS1572.  
The VDD pin is the power supply pin for the PLL synthesizer  
circuitry and other lower current digital functions. We recom-  
mend that RC decoupling or zener regulation be provided for  
this pin (as shown in the recommended application circuitry).  
This will allow the PLL to “track” through power supply  
fluctuations without visible effects. See Figure 7 for typical  
external circuitry.  
VCO Gain Programming: Use the minimum gain which  
can reliably achieve the VCO frequency desired, as shown  
here:  
VCO GAIN  
MAX FREQUENCY  
120 MHz  
200 MHz  
230 MHz  
*
4
5
6
7
* SPECIAL APPLICATION. Contact factory for custom product above  
230 MHz.  
Figure 6  
5
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