ICS1572
Overview
The
ICS1572
is ideally suited to provide the graphics system
clock signals required by high-performance video DACs.
Fully programmable feedback and reference divider capability
allow virtually any frequency to be generated, not just simple
multiples of the reference frequency. The
ICS1572
uses the
latest generation of frequency synthesis techniques developed
by ICS and is completely suitable for the most demanding
video applications.
PLL Post-Scaler
A programmable post-scaler may be inserted between the VCO
and the CLK+ and CLK- outputs of the
ICS1572.
This is useful
in generating of lower frequencies, as the VCO has been
optimized for high-frequency operation.
The post-scaler allows the selection of:
PLL Synthesizer Description -
Ratiometric Mode
The
ICS1572
generates its output frequencies using phase-
locked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency pro-
vided to the PLL (see Figure 1). The reference frequency is
generated by an on-chip crystal oscillator or the reference
frequency may be applied to the
ICS1572
from an external
frequency source.
The phase-frequency detector shown in the block diagram
drives the voltage-controlled oscillator, or VCO, to a frequency
that will cause the two inputs to the phase-frequency detector
to be matched in frequency and phase. This occurs when:
F(
VCO)
: =
F(XTAL1) . Feedback Divider
Reference Divider
•
•
•
•
VCO frequency
VCO frequency divided by 2
VCO frequency divided by 4
Internal register bit (AUXCLK) value
Load Clock Divider
The
ICS1572
has an additional programmable divider
(referred to in Figure 1 as the N1 divider) that is used to
generate the LOAD clock frequency for the video DAC. The
modulus of this divider may be set to 3, 4, 5, 6, 8, or 10 under
register control. The design of this divider permits the output
duty factor to be 50/50, even when an odd modulus is selected.
The input frequency to this divider is the output of the PLL
post-scaler described above.
Digital Inputs - ICS1572-101 Option
The AD0-AD3 pins and the STROBE pin are used to load all
control registers of the
ICS1572
(-101 option). The AD0-AD3
and STROBE pins are each equipped with a pull-up and will
be at a logic HIGH level when not connected. They may be
driven with standard TTL or CMOS logic families.
The address of the register to be loaded is latched from the
AD0-AD3 pins by a negative edge on the STROBE pin. The
data for that register is latched from the AD0-AD3 pins by a
positive edge on the STROBE pin. See Figure 2 for a timing
diagram. After power-up, the
ICS1572-101
requires 32 regis-
ter writes for new programming to become effective. Since
only 13 registers are used at present, the programming system
can perform 19 “dummy” writes to address 13 or 14 to com-
plete the sequence.
This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided
to the part (assuming correctly programmed dividers).
The VCO gain is programmable, which permits the
ICS1572
to
be optimized for best performance at all operating frequencies.
The reference divider may be programmed for any modulus
from 1 to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 391 in steps of one. Any even modulus from
392 through 782 can also be achieved by setting the “double”
bit which doubles the feedback divider modulus. The feedback
divider makes use of a dual-modulus prescaler technique that
allows the programmable counters to operate at low speed
without sacrificing resolution. This is an improvement over
conventional fixed prescaler architectures that typically im-
pose a factor-of-four penalty (or larger) in this respect.
Table 1 permits the derivation of “A” & “M” counter program-
ming directly from desired modulus.
2
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