ICS1572
Register Mapping - ICS1572-301 (Serial Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1572. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.
BIT(S)
1-3
BIT REF.
N1[0]..N1[2]
DESCRIPTION
Sets N1 modulus according to this table. These bits are set to implement
a divide-by-four on power-up.
N1[2]
0
0
0
0
1
1
1
1
N1[1]
0
0
1
1
0
0
1
1
N1[0]
0
1
0
1
0
1
0
1
RATIO
3
4
4
5
6
8
8
10
4
5
RESERVED
RESERVED
Set to zero.
MUST be set to zero.If this bit is ever programmed for a logic one, device
operation will cease and further serial data load into the registers will be
inhibited until a power-off/power-on sequence.
Tristates phase detector outputs, resets phase detector logic, and resets
R, A, M, and N2 counters.
Set to zero for normal operations. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+/−1 CLK period).
To initiate a RAMDAC reset sequence, simply write a one to this register
bit followed by a zero.
When set to logic 1, passes the reference frequency to the post-scaler.
Controls substitution of N1 and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the N1 and N2 dividers are used.
VRAM shift clock enable bit. When logic 1, the BLANK pin can be used
to disable the LD/N2 output.
External PLL feedback select. When logic 1, the EXTFBK pin is used for
the phase-frequency detector feedback input.
Phase detector reset enable control bit. When this bit is set, a high level
on the BLANK input will disable PLL locking. See LINE-LOCKED
CLOCK GENERATION section for more details on the operation of
this function.
6
7
JAMPLL
DACRST
8
9
10
11
12
SELXTAL
ALTLOOP
SCEN
EXTFBKEN
PDRSTEN
9
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
