ICS1572
This allows the synthesizer to be completely programmed for
the desired frequency before it is made active. Once the part
has been “unlocked” by the 32 writes, programming becomes
effective immediately.
ALL registers identified in the data sheet (0-9, 11, 12 & 15)
MUST be written upon initial programming. The programming
registers are not initialized upon power-up, but the latched
outputs of those registers are. The latch is made transparent
after 32 register writes. If any register has not been written, the
state upon power-up (random) will become effective. Registers
13 & 14 physically do not exist. Register 10 does exist, but is
reserved for future expansion. To insure compatibility with
possible future modifications to the database, ICS recommends
that all three unused locations be written with zero.
An additional control pin on the
ICS1572-301,
BLANK can
perform either of two functions. It may be used to disable the
phase-frequency detector in line-locked applications. Alterna-
tively, the BLANK pin may be used as a synchronous enable
for VRAM shift clock generation. See sections on Line-Locked
Operations and VRAM shift clock generation for details.
Output Description
The differential output drivers, CLK+ and CLK, are current-
mode and are designed to drive resistive terminations in a
complementary fashion. The outputs are current-sinking only,
with the amount of sink current programmable via the IPRG
pin. The sink current, which is steered to either CLK+ or CLK-,
is approximately four times the current supplied to the
IPRG
pin. For most applications, a resistor from VDDO to IPRG will
set the current to the necessary precision. See Figure 6 for
output characteristics.
The LOAD output is a high-current CMOS type drive whose
frequency is controlled by a programmable divider that may be
selected for a modulus of 3, 4, 5, 6, 8, or 10. It may also be
suppressed under register control.
The LD/N2 output is high-current CMOS type drive whose
frequency is derived from the LOAD output. The programma-
ble modulus may range from 1 to 512 in steps of one.
ICS1572-101 Register Loading
5
STROBE
1
AD0-AD3
2
3
DATA VALID
4
ADDRESS VALID
Figure 2
Digital Inputs - ICS1572-301 Option
The programming of the
ICS1572-301
is performed serially
by using the DATCLK, DATA, and HOLD~pins to load an
internal shift register.
DATA is shifted into the register on the rising edge of
DATCLK. The logic value on the HOLD~ pin is latched at the
same time. When HOLD~ is low, the shift register may be
loaded without disturbing the operation of the
ICS1572.
When
high, the shift register outputs are transferred to the control
registers, and the new programming information becomes ac-
tive. Ordinarily, a high level should be placed on the HOLD~
pin when the last data bit is presented. See Figure 3 for the
programming sequence.
ICS1572-301 Register Loading
8
DATCLK
6
DATA
HOLD
7
DATA_2
DATA_56
Pipeline Delay Reset Function
The
ICS1572
implements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACs. This se-
quence can be generated by setting the appropriate register bit
(DACRST) to a logic 1 and then resetting to logic 0.
When changing frequencies, it is advisable to allow 500 mi-
croseconds after the new frequency is selected to activate the
reset function. The output frequency of the synthesizer should
be stable enough at that point for the video DAC to correctly
execute its reset sequence. See Figure 4 for a diagram of the
pipeline delay reset sequence.
Pipeline Delay Reset Timing
STROBE
or
DATCLK
CLK+
DATA_1
10
9
11
T
CLK
LOAD
12
Figure 3
3
Figure 4
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
