ICS1531 参数 Datasheet PDF下载

型号：	ICS1531
PDF下载：	下载PDF文件查看货源
内容描述：	888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用：	转换器时钟发生器
文件页数/大小：	76 页 / 525 K
品牌：	ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]

ICS1531 Data Sheet - Preliminary

Chapter 6 Register Set

6.5.40.4 Register 3Bh: CAL_1

The CAL_1 Register is used to select (1) delays to calibrate the ADC data delay and (2) the clock delay for

the green and red channels.

Table 6-42. CAL1 Register

Bit

Bit Name

Bit Definition

Ac-

cess

Spec.

Func.

Re-

set

^R•^es^S^e^e^rv^e^e^S^d^e^.^{ction 6.1, “Reserved Bits”.}

• ^{This bit can be programmed to ‘0’.}

3B:7

Reserved

–

^A•^na^T^l^h^oⁱ^g^s^-^b^to^it^-^w^D^o^ig^rk^it^s^al^w^C^ith^on^R^v^e^e^g^r^s^te³^r^C^D^:4^at^a^aⁿ⁽^d^G³^l^C^ob^:3^al^f⁾^or^D^a^el^g^a^lo^y^b^[^a⁰^l^].^delay

3B:6

ADC_DD [0]

G_CD

See Reg

37:3

–

of all RGB data output from the ADC.

• ^{This bit is the least-significant bit.}

Green (Channel) Clock Delay.

3B:5-

3B:3

R/W

–

These bits select a delay (that is, an offset) for use in

calibrating the clock for the green channel. (An acknowledge See Reg

of these bits occurs only when the Calibration Regs are

37:3

^e•^na⁰^b^,^le^th^d^e^.)^c^W^lo^h^c^ekndt^e^h^l^e^a^s^y^e^c^b^aⁱ^l^t^ibsr^a^a^r^t^e^io^:^{n offset is 0.}

• ^{1 or above, the clock delay calibration offset increases.}

3B:2

3B:0

R_CD

Red (Channel) Clock Delay.

These bits select a delay (that is, an offset) for use in

R/W

calibrating the clock for the red channel. (An acknowledge of See Reg

these bits occurs only when the Calibration Regs are

37:3

^e•^na⁰^b^,^le^th^d^e^.)^c^W^lo^h^c^ekndt^e^h^l^e^a^s^y^e^c^b^aⁱ^l^t^ibsr^a^a^r^t^e^io^:^{n offset is 0.}

• ^{1 or above, the clock delay calibration offset increases.}

6.5.40.5 Register 3Ch: CAL_2

The CAL_2 Register is used to select (1) delays to calibrate the ADC data delay and (2) the clock delay for

blue channel.

Table 6-43. CAL2 Register

Bit

Bit Name

Bit Definition

Ac-

Spec. Re-

cess

Func.

set

3C:7-

3C:5

Bandgap_CAL Bandgap Calibration.

To calibrate the ICS1531 bandgap voltage, these bits adjust

R/W

–

the current to VRTR, VRTG, and VRTB. (An acknowledge

occurs only when the Test mode is enabled.)

^A•^na^T^lo^he^g^s^-t^e^o^b^-D^its^ig^w^it^o^a^r^l^k^C^w^oⁱⁿ^th^ve^R^r^e^te^g^r³^D^B^a^:6^ta^fo^(G^{r a}^lo^g^b^l^a^o^l^b⁾^a^D^{l d}^el^e^a^la^y^y^[2^o^-^f¹^a^]^l^.^l

3C:4-

3C:3

ADC_DD [2-1]

B_CD

See Reg

37:3

–

RGB data output from the ADC.

• ^{These bits are the most-significant bits.}

Blue (Channel) Clock Delay.

3C:2-

3C:0

R/W

These bits select a delay (that is, an offset) for use in

calibrating the clock for the blue channel. (An acknowledge See Reg

of these bits occurs only when the Calibration Regs are

enabled.) When these bits are:

37:3

• ^{0, the clock delay calibration offset is 0.}

• ^{1 or above, the clock delay calibration offset increases.}

ICS1531 Rev N 12/1/99

December, 1999

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