ICS1531 Data Sheet - Preliminary
Chapter 7 Programming
7.2 Programming Flow for Modifying PLL and DPA Settings
Figure 7-2. ICS1531 Flow for Capture/Input Clock PLL
Initialize
Registers 0 and 8
Set DPA Output
Reg4[5:0]=0
Delay to 0
Change
PLL Freq.
No
Yes
?
Regs 0 through 3
Set Input, PFD Gain, Post
Scaler, and Feedback Divider
PLL Software Reset
RegA=50h
Wait ~1ms
PLL
Locked
No
Reg12[1]=1?
?
Yes
Set DPA
Resolution
DPA Software Reset
Wait ~1ms
RegA=0Ah
Select Desired
DPA Output Delay
Reg4[5:0]
Enable
Desired Outputs
Reg6[6:2]
Done
ICS1531 Rev N 12/1/99
December, 1999
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
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