ICS1531 参数 Datasheet PDF下载

型号：	ICS1531
PDF下载：	下载PDF文件查看货源
内容描述：	888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用：	转换器时钟发生器
文件页数/大小：	76 页 / 525 K
品牌：	ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]

ICS1531 Data Sheet - Preliminary

Chapter 6 Register Set

6.5 Register Definitions

The tables in this section specify for each register bit the reset value, if one exists. After a reset, the

ICS1531 sets all register bits to their default values.

Note:

1. For the reserved bits, see Section 6.1, “Reserved Bits”.

2. For Register Set conventions, see Section 6.2, “Register Set Conventions”.

3. For acronyms used in this table, see Section 6.3, “Register Set Abbreviations and Acronyms”.

6.5.1 Register 00h: Input Control Register

The Input Control Register is used to select inputs that control the pixel PLL Phase/Frequency Detector.

Table 6-3. Input Control Register

Bit

Bit Name

Bit Definition

Ac- Spec. Re-

cess Func.

set

00:7- HSYNC_Sel [1-0] Horizontal Sync Select [1-0].

–

00:6

These multiplexed bits select one of possible four Schmitt

^tr•^igg⁰^e⁼^rs^S^th^ch^a^m^{t c}^it^o^tⁿ^trⁿ^ig^e^g^ct^e^t^r^o⁰^{the input HSYNC pin.}

• ^{1 = Schmitt trigger 1}

• ^{2 = Schmitt trigger 2. (Recommended setting.)}

• ^{3 = Schmitt trigger 3}

00:5

00:4

00:3

In_Sel

Input Select.

–

^T•^his⁰^b⁼^it^T^s^h^e^e^leⁱ^cⁿ^t^p^s^u^a^tⁿ^isⁱⁿ^H^p^S^u^Y^{t t}^N^o^C^{th. e Phase/Frequency Detector.}

• ^{1 = The input is OSC (default).}

Fdbk Div Load

Fdbk_Pol

Feedback Divider Load Control.

R/W

^T•^his⁰^b⁼^it^T^s^h^e^e^le^l^c^o^t^a^s^d^a^is^lo^o^aⁿ^d^t^f^h^o^e^{r t}^phi^e^xeⁱⁿ^l^t^P^e^L^rn^L^a^r^l^e^f^s^e^eet^d^.^{back divider.}

• ^{1 = The load is on the next scan line.}

Feedback Polarity.

This bit selects the polarity of the feedback signal to the

^P•^ha⁰^se⁼^/^T^F^h^re^e^q^p^u^o^e^lⁿ^a^c^ri^y^ty^D^is^et^p^e^o^c^s^to^it^r^{iv. e edge.}

• ^{1 = The polarity is negative edge.}

00:2

00:1

Ref_Pol

PD_Pol

(External) Reference Polarity.

This bit selects the polarity of REF, the reference signal

provided by the input HSYNC to the Phase/Frequency

^D•^ete⁰^c⁼^to^T^r^{.he polarity is positive edge.}

• ^{1 = The polarity is negative edge.}

R/W

–

Phase/(Frequency) Detector Polarity.

This bit selects the polarity of the PDEN signal to the

^P•^ha⁰^se⁼^/F^T^r^h^e^e^qu^s^e^ignncayl^D^fro^e^m^tec^th^to^e^r^{.PDEN pin is active high.}

• ^{1 = The signal from the PDEN pin is active low.}

Note:

This bit is disabled when Reg 00:0 = 1.

ICS1531 Rev N 12/1/99

December, 1999

电子百科

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