ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.4 Register Set Outline
Table 6-2 outlines the ICS1531 Register Set.
Note:
1. For the reserved bits, see Section 6.1, “Reserved Bits”.
2. For abbreviations and acronyms, see Section 6.3, “Register Set Abbreviations and Acronyms”.
Table 6-2. Register Set Outline
Register Register Name
Index
Register
Access
R/W
Bit #
Bit Name
Brief Description
Select a Schmitt trigger
Reset
Value
0
1
0
0
00h
Input Control
7-6 HSYNC_Sel
5
4
3
In_Sel
Fdbk Div Load
Fdbk_Pol
Select input
Select load for Feedback Divider
Select polarity of feedback to Phase/Frequency
Detector
2
1
0
Ref_Pol
PD_Pol
PD_En
Select polarity of external reference
Select polarity of PDEN to Phase/Frequency Detector
Enable Phase/Frequency Detector
0
0
1
01h
Loop Control
R/W. D-PLL.
7-6 Reserved
5-4 PSD
Reserved
Select value for Post-Scaler Divider
Reserved
0
0
0
0
3
Reserved
2-0 PFD
Select Phase/Frequency Detector gain
02h
03h
Fdbk Div 0
Fdbk Div 1
R/W. D-PLL.
R/W. D-PLL.
7-0 FDBK [7-0]
Select value for Feedback Divider LSBs bits 7-0
FF
7-4 Reserved
3-0 FDBK [11-8]
Reserved
–
0
Select value for Feedback Divider MSBs bits 11-8
04h
05h
06h
DPA Offset
R/W
7-6 Reserved
5-0 DPA_OS
Reserved
0
0
Select offset for Dynamic Phase Adjust
DPA Control
R/W. D-DPA. 7-2 Reserved
1-0 DPA_Res
Reserved
–
0
Select resolution for Dynamic Phase Adjust
Output Enables R/W
7
6
5
4
3
2
Reserved
OE_Tck
OE_ADCRCLK
OE_ADCSYNC
FUNC_Sel
Reserved
0
0
0
0
0
0
0
Enable clock output to ADC
Enable clock output from ADC
Enable output for delayed ADCSYNC
Select signal source for ADC_FUNC signal
Select delay for ADC_FUNC signal
Reserved
FUNC_Delay
1-0 Reserved
07h
08h
OSC Divider
Internal Filter
R/W
R/W
7-0 OSC_Div
Specify value for oscillator divider
0
7
Shunt_Sel
Select internal filter shunt capacitor size
Select internal filter resistor size
Select internal filter capacitor size
Select type of loop filter
1
7
7
1
6-4 Res_Sel
3-1 Cap_Sel
0
Fil_Sel
09h
0Ah
Reserved
N/A
N/A
Pixel PLL
Reset/
Write
7-4 Pixel PLL Reset Writing 5xh resets pixel PLL and loads working Regs
1h through 3h
DPA Reset
3-0 DPA Reset
Writing xAh resets DPA and loads working Reg 5h
N/A
N/A
0Bh-0Fh Reserved
ICS1531 Rev N 12/1/99
December, 1999
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
24
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