iC-JX
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE
Rev C1, Page 23/36
Control Word 3A (flash pulse settings)
Adr. 0x18
Reset-Zustand : 0x00
Nibble 3:
I/O-Pins 13..16
Nibble 2:
I/O-Pins 9..12
Nibble 1:
I/O-Pins 5..8
Nibble 0:
I/O-Pins 1..4
Bit
7
6
5
4
3
2
1
0
Name
Nibble 1
PN31
PN30
PN21
PN20
PN11
PN10
PN01
PN00
Nibble3, Bit7..6
Nibble2, Bit5..4
Nibble1, Bit3..2
Nibble0, Bit1..0
PN31
PN21
PN11
PN01
0
0
1
1
PN30
PN20
PN10
PN00
0
1
0
1
Flash frequency
Flash frequency
SEBLQ = 0
f(BLFQ)
f(BLFQ/2)
f(BLFQ/4)
f(BLFQ/16)
SEBLQ = 11
f(SECLK)/219
f(SECLK)/220
f(SECLK)/221
f(SECLK)/223
(r)
1. SEBLQ: see control word 3B
Control Word 3B (reference clock)
Adr. 0x19
reset entry: 0x00
0
Bit
7
-
6
-
5
-
4
-
3
2
1
-
Name
SECLK1
SECLK0
SEBLQ
Bit0
SEBLQ
Settings for flash frequency
SEBLQ
0
1
The flashing pulse is derived from the external clock signal at BLFQ
The flashing pulse is derived from the system clock SECLK
(r)
(r)
Bit3..2
SECLK1..0 0
SECLK1
SECLK0
Settings for system clock SECLK
0
1
0
1
Operation with the clock signal at CLK
Operation with the internal clock signal ICLK
Operation without the clock signal at CLK (filterung etc. deactivated)
reserved
0
1
1
ICHAUS [ IC-HAUS GMBH ]
