IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
5. Register Descriptions
This section describes the registers, including field definitions, that provide the mechanism for
PowerPRS Q-64G configuration specification and status reporting.
Table 5-1 identifies each register and provides the page number where the corresponding description is
located. In the register descriptions, reserved bits and addresses are not implemented. Reserved bits return
‘0’ when read and ignore all write values.
Registers x‘01’ to x‘08’ are implemented in the serial host interface (SHI) logic and are reset by activating the
PowerOnResetIn# input signal. These registers can be accessed before the phase-locked loop (PLL) is
started or the flush is complete. All the bits in the remaining registers are set to ‘0’ during a flush, unless
otherwise specified.
Note: In the 256-Gbps internal speed expansion configuration, the ports in each of the four
PowerPRS Q-64Gs are paired as follows: physical ports 0 and 1 are paired to form logical port 0, physical
ports 2 and 3 are paired to form logical port 1, and so forth. Because all the registers report physical informa-
tion, information to or from logical queue L is reported using bit L × 2 for the registers in which a bit corre-
sponds to a port. For example, to enable the output queue for logical port 3, bit 6 in the Output Queue Enable
Register (page 124) must be set.
Table 5-1. Register Map (Page 1 of 4)
Register Name
Address
Access
Page
Reserved for no-op operation
x‘00’
SHI Internal Registers: x‘01’ to x‘08’
Internal PLL Programming Register
Internal PLL Status Register
Unilink PLL Programming Register
Unilink PLL Status Register
Reset Register
x‘01’
x‘02’
x‘03’
x‘04’
x‘05’
x‘06’
x‘07’
x‘08’
Read/Write
Read Only
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
67
67
68
68
69
70
70
71
BIST Counter Register
BIST Data Register
BIST Select Register
Unilink Programming Registers: x‘09’ to x‘32’
UL Global Register
x‘09’
x‘0A’
x‘0B’
x‘0C’
x‘0D’
x‘0E’
x‘0F’
x‘10’
Read/Write
Read Only
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
72
74
76
78
78
79
80
80
UL Errors Register
UL PLL Unlock Register
UL TxPort Driver Enable Register
UL TxPort Attachment Enable Register
UL TxPort Parameters Register
UL TxPort BIST Request Register
UL TxPort BIST Error Register
prsq-64g.01.fm
December 20, 2001
Register Descriptions
Page 63 of 199
IBM [ IBM ]
