IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
4. Programming Interface
The serial host interface (SHI) is the programming interface between the local processor and the
PowerPRS Q-64G. It provides access to all PowerPRS Q-64G internal resources through four signals:
• SHIClockIn:
• SHISelectIn#
• SHISerialDataIn
• SHISerialDataOut
The SHI and the SHI internal logic are synchronized to the SHI clock, which is asynchronous to the system
clock (see Section 7.2.2 SHI Signals on page 166). The SHI Instruction Register and the power-on registers
(addresses x‘01’ to x‘08’) are reset when the PowerOnResetIn# signal is activated.
4.1 SHI Instruction Register
An instruction scanned into the SHI is decoded into four parts:
• Data field (32 bits)
• Address field (7 bits)
• OpCode bit
• Parity bit
Address
Data (32)
SHISerialDataIn
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
...
40
0
1
SHISerialDataOut
Computed Parity
Send Parity
Bit(s)
0
Field Name
Parity
Description
If the parity is correct, executes the instruction. If the parity is incorrect, inhibits the instruction.
Specifies the SHI command to be executed. See Table 4-1 for descriptions of these commands.
Specifies the internal register to be read or written.
1
OpCode
Address
Data (32)
2:8
9:40
Contains the value that will be written or the value that has been returned.
prsq-64g.01.fm
December 20, 2001
Programming Interface
Page 61 of 199
IBM [ IBM ]
