IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
1. Rerouting traffic to one switch plane
2. Modifying the load-balancing configuration
3. Resuming traffic on both switch planes
The scheduled switchover process for the active/backup initial operating condition is very similar. Minor differ-
ences are identified below.
3.11.1.1 Phase 1: Rerouting Traffic to One Switch Plane
Before the scheduled switchover begins, data traffic is routed through both switch planes under the load-
balancing configuration specified in the Bitmap Filter Registers. During phase 1 of the switchover process,
traffic is rerouted so that it flows through only one switch plane. For this discussion, the Y switch plane is
dropped and the X switch plane remains active. Phase 1 is initiated on red traffic and is complete when all
traffic is blue.
To reroute traffic to one switch plane:
1. Because all current traffic (idle and data) is red, the local processor configures each PowerPRS Q-64G to
detect the color blue by changing the expected color bit and issuing a color clear command.
2. All ingress devices change the packet qualifier byte of their incoming packets to change the color from red
(normal traffic) to blue (no filtering). In addition:
• On the Y path, the ingress devices send all their buffered red data packets to the switch core, and
then start generating blue idle packets to the switch core.
• On the X path, all ingress devices send all their buffered red packets (regardless of priority) to the
switch core, and then begin sending their blue data packets to the switch core.
Simultaneously, the egress devices block data packet reception from the X switch plane by locking their
peer buffer (which connects the X and Y paths). This prevents blue traffic reception before red traffic is
fully exhausted. (If the switch planes were operating in an active/backup condition, this switch plane
would be the backup, and the only traffic would be link-liveness packets.)
3. When at least one blue packet (idle or data) has been received on each active input port of the X or Y
switch plane, then all the red data packets have been delivered to that switch plane and all the active
input ports will be receiving only blue packets (either idle or data). Each of the two local processors
attached to the serial host interface (SHI) is informed, through polling, that its switch core is detecting only
blue packets.
Note: The Expected Color Received Register (page 126) reports the receipt of a blue packet since the
last color clear command on each port that has not been tagged as inactive by the Color Detection Dis-
able Register (page 125). The color blue was set by the expected color bit. When all bits are set in the
Expected Color Received Register, the switch core is detecting only blue packets.
4. On the Y switch plane, when at least one blue packet has been detected on each active input port and
output queue n is empty, the PowerPRS Q-64G begins to continuously generate blue (rather than red)
idle packets to port n. On the X switch plane, when at least one blue packet has been detected on each
active input port, the PowerPRS Q-64G begins generating blue (rather than red) idle packets, as neces-
sary.
At this point, all egress packets from both switch planes are blue (idle packets or data packets on the
X path, and idle packets on the Y path). All data traffic is blue (unfiltered) and carried on the X path.
5. When all active egress devices have detected the arrival of a blue idle packet from the Y switch core and
these devices have no more packets to send from their packet buffer queue for that switch plane to the
prsq-64g.01.fm
December 20, 2001
Functional Description
Page 59 of 199
IBM [ IBM ]
