IBM PowerPRS Q-64G
Packet Routing Switch
Preliminary
attached traffic manager, then they unlock their peer buffer. This step unblocks traffic transmission from
the X switch plane, which has blue packets waiting for transmission to the attached devices.
Phase 1 of the switchover is complete for the entire switch fabric. The egress devices convey this status
to their attached processor.
3.11.1.2 Phase 2: Modifying the Load-Balancing Configuration
When phase 1 of the scheduled switchover is complete, all traffic through both switch planes is blue and data
traffic flows through only one plane. Both local processors can now safely modify the content of the Bitmap
Filter Register (page 125) in accordance with the new configuration parameters, which may specify new port
assignments for a different load-balancing configuration.
3.11.1.3 Phase 3: Resuming Traffic on Both Switch Planes
Phase 3 of the switchover starts the new load-balancing configuration. This phase is similar to phase 1,
except it is initiated on blue traffic and is complete when all traffic is red. For this discussion, the Y switch
plane is dropped and the X switch plane remains active. During phase 3, split traffic is resumed on both
switch planes.
To resume traffic on both switch planes:
1. Because all current traffic (idle and data) is blue, the local processor configures each PowerPRS Q-64G
to detect the color red by changing the expected color bit and issuing a color clear command.
2. All ingress devices stop changing the packet qualifier byte of their incoming packets so that the packet
color remains red. In addition:
• On the Y path, all ingress devices start generating red (rather than blue) idle packets to the switch
core.
• On the X path, all ingress devices send all their buffered blue packets (regardless of priority) to the
switch core, and then begin sending their red data packets to the switch core.
Simultaneously, the egress devices block data packet reception from the Y switch plane by locking their
peer buffer. This step prevents red traffic reception before blue traffic is fully exhausted.
3. When at least one red packet (idle or data) has been received on each active input port of the X or Y
switch plane, then all the blue data packets have been delivered to that switch plane and all the active
input ports will be receiving only red packets (either idle or data). Each of the two local processors
attached to the SHI is informed, through polling, that its switch core is detecting only red packets.
4. On each switch plane, when at least one red packet has been detected on each active input port, the
PowerPRS Q-64G on that switch plane begins to generate red (rather than blue) idle packets, as
necessary. At this point, all egress packets from both switch planes are red.
5. When all active egress devices have detected the arrival of a red idle packet from the X switch core and
these devices have no more packets to send from their packet buffer queue for that switch plane to the
attached traffic manager, then they unlock their peer buffer. This step unblocks traffic transmission from
the Y switch plane, which has red packets waiting for transmission to the attached devices.
Switchover is complete for the entire switch fabric. The egress devices convey this status to their
attached processor.
Functional Description
Page 60 of 199
prsq-64g.01.fm
December 20, 2001
IBM [ IBM ]
