IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
8 to 15 port range. In the 512-Gbps configuration, all destination output ports must be within the 0 to 15 port
range or the 16 to 31 port range. If an ingress packet destination bitmap contains output ports in both ranges,
the attached device duplicates the packet. Each output port transmits a multicast packet according to a first-
first-out queuing structure and, consequently, the multicast packet is not necessarily transmitted at the same
time on every port. A multicast packet has only one priority, which applies to all its destinations.
3.8.1 Data Packet Reception
PowerPRS Q-64G input controllers discard an ingress data packet when:
• All packet destination output ports are disabled.
• The input controller does not have a store address available for packet storage in the shared memory.
This flow control error is reported via the no address interrupt bit in the Status Register (page 120). This
bit generates an interrupt unless the error is masked with the corresponding no address interrupt bit in
the Interrupt Mask Register (page 122). This error occurs only if the shared memory threshold is pro-
grammed incorrectly, or if the attached device does not respond to the memory grant information.
• Output queue grants or memory grants have not been issued, as required. This flow control error is
reported via the flow control violation bit in the Status Register (page 120). This bit generates an interrupt
unless the error is masked with the corresponding flow control violation bit in the Interrupt Mask Register
(page 122). This error occurs only if the attached device does not respond to the ingress flow control
information.
• The destination bitmap value is all zeros after packet filtering.
• The input controller best-effort discard filter is enabled and the discard condition is met (see Section
3.4.6.3 Best-Effort Discard Filters on page 51).
3.8.2 Control and Service Packet Reception
When the PowerPRS Q-64G receives a control packet or command service packet, the packet is stored in
input controller internal registers (each input controller can store one control packet or command service
packet per channel). The bit corresponding to the input port is set in the appropriate Ingress Control Packet or
Command Service Packet Received Register (page 136), and the control packet received or command
service packet received bit is set in the Status Register. After the packet payload is transferred to the local
processor using the Ingress Control Packet and Service Packet Source Register (page 137) and the Ingress
Control Packet and Service Packet Payload Registers (page 138), a new control packet or command service
packet can be stored. If an input controller receives a control packet or command service packet before the
previous one has been processed, the input controller discards the incoming packet and sets the control
packet discard bit or command service packet discard bit in the Status Register.
When the PowerPRS Q-64G receives an event service packet, the bit corresponding to the input port is set in
the appropriate Ingress Event Service Packet Received Register (page 139). When the value of the Ingress
Event Service Packet Received Register is equal to the value of the Ingress Event Service Packet Mask
Register (page 139), the appropriate “all event service packets received” bit is set in the Status Register
(page 120).
prsq-64g.01.fm
December 20, 2001
Functional Description
Page 55 of 199
IBM [ IBM ]
