IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
address pool. After the packet is transmitted, the output queue returns the address to the address manager,
which returns it to the available address pool. For multicast packets, one store address is sent to multiple
output queues. The address manager tracks the number of output queues holding each store address and,
when the count reaches zero, returns the address to the available shared memory address pool.
2.2.5 Input Controllers
The PowerPRS Q-64G has 32 input controllers, one input controller per port. Each input controller processes
two packets at a time, one packet on the high channel and one packet on the low channel. When a packet
arrives, the input controller of the master device extracts the header information (including packet priority and
destination) from the master LU. It checks the master LU header integrity using a parity bit on the header
bytes. If the packet is valid, the input controller stores it in the shared memory when access is granted by the
sequencer.
An input controller stores a packet in the shared memory of one of its two subswitch elements, depending on
the packet’s destination. Packets stored in subswitch elements A and C are destined for output ports 0 to 15,
and packets stored in subswitch elements B and D are destined for output ports 16 to 31 (see Figure 2-2).
The input controller uses the store address provided by the address manager of the subswitch element. The
input controller also forwards the shared memory address, packet priority, and packet destination to the out-
put queue access manager. Packets arrive with a priority of 0 to 3, with 0 being the highest priority. Note that
multicast packets have only one priority for all destinations.
In multiple-device configurations, the input controller on the master device forwards information such as the
shared memory store address and subswitch element ID to the input controllers on the slave devices.
2.2.6 Output Queue Access Managers
Each subswitch element has an output queue access manager that receives the packet store address,
priority, and destination from the input controllers and forwards the information to the output queues for the
subswitch element. Each output queue access manager also maintains the counters that the
PowerPRS Q-64G uses to control ingress traffic flow. For each output queue, a counter tracks the total
number of packets enqueued for that output, regardless of priority. Another counter tracks the total number of
packets stored in the shared memory, regardless of output or priority.
2.2.7 Output Queues
The output queues contain the shared memory addresses of packets awaiting transmission from the
PowerPRS Q-64G. In each of the four subswitch elements, each of the 16 output ports has one output queue
per priority. Each output queue is organized into two address banks: one bank holds addresses written by
even ports and the other bank holds addresses written by odd ports. Packet addresses are organized in a
first-in-first-out (FIFO) queuing structure in each address bank. Each output queue can store up to 1024
addresses.
A unicast packet address is stored in one output queue, and a multicast packet address is stored in two or
more output queues.
prsq-64g.01.fm
Architecture
December 20, 2001
Page 19 of 199
IBM [ IBM ]
