IBM PowerPRS Q-64G
Packet Routing Switch
Preliminary
2.2.8 Output Queue Scheduler and Credit Table
The output queue scheduler determines which output queue will provide the next egress packet retrieve
address and notifies each selected output queue in turn. Each selected output queue then forwards its next
retrieve address to the shared memory.
The output queue scheduler selects an output queue using several pieces of information. For each subswitch
element output port, the output queues provide an output queue status (that is, output queue empty), one per
priority, to the output queue scheduler. The output queue scheduler also receives the send grants that control
egress traffic flow to the attached devices. In general, the output queue scheduler selects the highest-priority
of the occupied output queues (so that high-priority packets overtake low-priority packets). However, a fixed
amount of bandwidth can be assigned to low-priority packets by altering priority scheduling in the credit table
(see Section 3.5.3 Credit Table on page 53).
Note: As discussed in Section 2.2.7, each output queue contains two address banks (those written by even
ports and those written by odd ports). If both address banks are occupied for a single priority, the output
queue scheduler toggles between the two banks to select and notify the entire output queue. Packet
addresses are processed on a FIFO basis within an address bank.
2.2.9 Output Controllers
The PowerPRS Q-64G has 32 output controllers, one output controller per port. Each port transmits two
packets at a time, one packet on the high channel and one packet on the low channel. When access is
granted by the sequencer, the output controller retrieves the next two packets to be transmitted on a port from
the retrieve addresses that the output queue scheduler forwarded to the shared memory. The output
controller inserts ingress and subport flow control information (that is, it inserts the grants) into the packet
header before forwarding the packets to the physical interface for serialization.
Note that each output controller retrieves packets from two 16 × 16 subswitch elements and merges the
traffic to a single output port. Output controllers 0 to 15 transmit from subswitch elements A and C; output
controllers 16 to 31 transmit from subswitch elements B and D (see Figure 2-2 on page 16).
2.3 Multiple-Device Configurations
The PowerPRS Q-64G is designed to provide OC-192 attachment. To meet these transmission requirements
and provide 16-Gbps throughput per port, multiple PowerPRS Q-64Gs are configured for speed expansion.
There are two standard multiple-device configurations:
• 512-Gbps configuration (eight devices that provide 32 input and output ports)
• 256-Gbps configuration (four devices that provide 16 input and output ports)
In both of these multiple-device configurations, one device is the master and the rest of the devices are
slaves. The master device performs packet routing and queueing and forwards packet synchronization and
shared memory address information to the slave devices. Because the slave devices only store slave LUs
and do not perform packet routing or queuing, their control sections are inactive to minimize power
consumption.
Table 2-1 on page 21 presents some of the features, including the shared memory capacity, of the two stan-
dard multiple-device configurations. Descriptions of these two configurations follow.
Architecture
prsq-64g.01.fm
December 20, 2001
Page 20 of 199
IBM [ IBM ]
