IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
Figure 2-5. 256-Gbps Configuration (internal and external speed expansion)
0
1
0
1
Slave Device
Memory
30
31
30
31
Control
Addresses
0
Port 0
(16 Gbps)
Port 0
(16 Gbps)
0
1
Slave Device
1
Memory
Control
30
31
30
31
16 Inputs
16 Outputs
(256-Gbps
aggregate
throughput)
(256-Gbps
aggregate
throughput)
Addresses
0
0
1
Slave Device
1
Port 15
(16 Gbps)
Port 15
(16 Gbps)
Memory
Control
30
31
30
31
Addresses
0
1
0
1
Master Device
Memory
Control
30
31
30
31
2.3.3.2 Shared Memory Addresses
When multiple devices are configured for external speed expansion, the input and output controllers of the
master device forward shared memory addresses to the input and output controllers of the slave devices. The
master device conveys this information via two speed-expansion buses:
• SpexDataIn is the speed-expansion bus that enters each slave device. It is comprised of eight Unilinks for
ingress addresses and eight Unilinks for egress addresses.
• SpexDataOut is the speed-expansion bus that exits the master device and all but the last slave device. It
is also comprised of eight Unilinks for ingress addresses and eight Unilinks for egress addresses.
The devices are connected serially to the speed-expansion buses. The master device generates addresses
and provides them to the first slave device. The first slave device then conveys the addresses to the next
slave device, and so forth, until the last slave device receives the addresses.
prsq-64g.01.fm
Architecture
December 20, 2001
Page 23 of 199
IBM [ IBM ]
