IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
Figure 2-3. 16 × 16 Subswitch Element Block Diagram
Port 0
Port 0
Store Addresses + Data
Data
Shared Memory
(1024 10-Byte Rows)
Ingress Flow
Egress Flow
Retrieve Addresses
Addresses + Priority
Output
Queues
Output Queue
Access Manager
(one per port
and per priority)
Port 15
Port 15
Address
Manager
Release Address
16
× 16 Subswitch Element
Sequencer
Output Queue Scheduler
The main components of the PowerPRS Q-64G are:
• Thirty-two input controllers
• Thirty-two output controllers
• Four self-routing subswitch elements, each housing a shared memory bank and a control section
comprised of:
- One address manager
- One output queue access manager
- Sixteen output queues (one per output port)
• Device control section, which includes a:
- Sequencer
- Output queue scheduler
- Credit table
• Unilink interface between the PowerPRS Q-64G and attached devices
2.2.1 Unilink Interface
The physical links between the PowerPRS Q-64G and attached devices are high-speed serial links called
Unilinks. The Unilink physical interface minimizes the number of pins. There is one Unilink per
PowerPRS Q-64G device port, or 32 Unilinks per device. Each Unilink is comprised of two pairs of differential
prsq-64g.01.fm
Architecture
December 20, 2001
Page 17 of 199
IBM [ IBM ]
