IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
Table 2-1. Multiple-Device Configuration Summary
Number of Port Speed Packet Length
LU Size
(bytes)
Shared Memory
Capacity (packets)
Device Configuration
Ports
(Gbps)
(bytes)
512-Gbps configuration
(eight devices with external speed expansion)
32 × 32
16
64, 72, or 80 8, 9, or 10
64, 72, or 80 8, 9, or 10
4096
2048
256-Gbps configuration
(four devices with internal and external speed expansion)
16 × 16
16
2.3.1 512-Gbps Configuration
In the 512-Gbps configuration, eight PowerPRS Q-64Gs are configured for external speed expansion (see
Figure 2-4). For external speed expansion, multiple devices are connected in parallel and the like-numbered
ports on all the devices are grouped. The total number of ports remains the same as on a single device, but
the throughput per port equals the throughput per port for a single device times the number of devices. A
single PowerPRS Q-64G features 32 ports at 2 Gbps per port; therefore, this configuration provides 32 ports
at 16 Gbps per port (for an aggregate throughput of 512 Gbps). In this configuration, the eight devices are
assembled on two switch cards.
2.3.2 256-Gbps Configuration
In the 256-Gbps configuration, four PowerPRS Q-64Gs are configured for both internal and external speed
expansion (see Figure 2-5 on page 23). For internal speed expansion, two ports within a device are paired.
This doubles the port speed but halves the number of ports. Because a single PowerPRS Q-64G features
32 ports at 2 Gbps per port, this configuration provides 16 ports at 16 Gbps per port (for an aggregate
throughput of 256 Gbps). In this configuration, the four devices are assembled on one switch card.
2.3.3 Master/Slave Synchronization with Multiple Devices
2.3.3.1 Sequencers
Each PowerPRS Q-64G contains a sequencer. When multiple devices are configured for external speed
expansion, the slave device sequencers must be synchronized to the master device sequencer to ensure that
the LUs for a particular port (or packet) are processed at the same time on all the devices. This synchroniza-
tion is done with the SyncIn (slave device input) and SyncOut (master device output) pins. The SyncIn/Out
pin mode bit in the Configuration 1 Register (page 112) sets the operating mode for these pins.
Note: In the 256-Gbps and 512-Gbps configurations, LU (and packet) transmission requires one sequencer
cycle.
prsq-64g.01.fm
Architecture
December 20, 2001
Page 21 of 199
IBM [ IBM ]
