IBM PowerPRS Q-64G
Packet Routing Switch
Preliminary
lines; one differential pair carries ingress flow and the other differential pair carries egress flow. Each pair of
differential lines (that is, each device port) carries two packets and has a total throughput of 2 Gbps. There-
fore, each Unilink carries two ingress packets and two egress packets at a time. The PowerPRS Q-64G phys-
ical interface carries the two ingress or two egress packets in separate streams; one packet is carried on the
high channel and one packet is carried on the low channel. See Section 3.2 Physical Interface and Packet
Processing on page 26 for more information.
2.2.2 Shared Memory
Each PowerPRS Q-64G device includes four 16 × 16 self-routing subswitch elements, denoted A, B, C, and
D (see Figure 2-2). The four subswitch elements house the shared memory, which stores the packets that the
PowerPRS Q-64G has received but has not yet transmitted. The shared memory on each subswitch element
consists of 1024 10-byte rows, and has two read ports and two write ports.
Subswitch elements A and B store packets from input ports 0 to 15, and subswitch elements C and D store
packets from input ports 16 to 31. For port expansion, each pair of subswitch elements is connected inter-
nally; that is, they are connected in parallel, in a single stage, to increase the number of ports without
changing the port speed. This provides the 32 × 32-port device configuration. The high subswitch elements
(A and C) store packets destined for output ports 0 to 15, and the low subswitch elements (B and D) store
packets destined for output ports 16 to 31 (see Figure 2-2 on page 16).
2.2.3 Sequencer
The sequencer controls the PowerPRS Q-64G internal data flow by granting shared memory access to the
input and output ports. Sequencer operation is based on time-division multiplexing (TDM). The sequencer
cycles concurrently among the input and output ports, granting shared memory access to two input ports and
two output ports at a time (one from ports 0 to 15 and one from ports 16 to 31) and visiting each port once per
cycle. During each shared memory access, one packet is transmitted to or from each of the port’s two
subswitch elements.
Packets are transmitted and stored in equal lengths called logical units (LUs). The standard
PowerPRS Q-64G configurations include either four or eight devices, in which one device is the master and
the rest of the devices are slaves. In these configurations, packets are divided into eight LUs (one master LU
and seven slave LUs) and distributed over all the devices.
During each shared memory access, 8 to 10 bytes of data are processed (read or written) per subswitch
element, depending on packet length. In the standard multiple-device configurations, processing an entire
LU requires one shared memory access. The sequencer cycle equals the time required to process the data
associated with one shared memory access. All sequencer cycles are equal in length.
The sequencer ensures that packets on a given port are always processed at a fixed interval according to
their LU length; therefore, no synchronization is required between input ports. The slave device sequencers
are synchronized to the master device sequencer so that all the LUs for a particular port (or packet) are pro-
cessed at the same time. See Section 2.3.3 Master/Slave Synchronization with Multiple Devices on page 21
for more information.
2.2.4 Address Managers
Each subswitch element has an address manager that tracks the available shared memory addresses on
the subswitch element and provides new store addresses to the input controllers. When an address manager
provides a store address to an input controller, it removes that address from the available shared memory
Architecture
prsq-64g.01.fm
December 20, 2001
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