IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
1. General Information
1.1 Features
• Nonblocking, self-routing, single-stage switch
• Either 16 or 32 input and output ports
• High performance:
• Support for redundant switch-plane operation,
including a scheduled switchover facility that
operates without packet loss
• Serial processor interface (serial host interface)
• Packet header of two or three bytes, containing
destination bitmap, packet priority, and switch
redundancy support information, all protected
by a parity bit
- Throughput of 2 Gbps per port without
speed expansion
- Aggregate throughput of up to 64 Gbps
for one device
• Speed expansion:
• Shared memory comprised of a dynamically
shared buffer with a total capacity of:
- Up to 4096 packets of 64, 72, or 80 bytes
for eight devices
- Up to 2048 packets of 64, 72, or 80 bytes
for four devices
• 8b/10b encoding for link synchronization and
supervision
• Reception of control packets destined for the
local processor on any input port
• Transmission of control packets from the local
processor to any output port
• Detection of link liveness by reception of specific
packets
- 16-Gbps logical interface using multiple
devices configured for speed expansion
- 512-Gbps aggregate throughput for eight
devices configured for external speed
expansion (32 ports at 16 Gbps)
- 256-Gbps aggregate throughput for four
devices configured for internal and external
speed expansion (16 ports at 16 Gbps)
- Other configurations (employing up to
seven devices) can be used in specific
applications
• Serial data communication of up to 2.5 Gbps,
compatible with InfiniBand physical layer
standards
• Programmable byte shuffling in egress packets
• CMOS 7SF (SA-27E) technology (Ldrawn = 0.18
µm, Leff = 0.11 µm): 1.8-V LVCMOS-compatible
I/O for low-speed signals
• Multicast support without packet duplication
in the shared memory
• Configurable number of traffic priorities (from
one to four)
• Flow control based on a grant mechanism
• Programmable flow control thresholds
• Subport flow control support
• IEEE® Standard 1149.1 boundary scan to facili-
tate circuit-board testing
• 624-ball IBM HyperBGA package
1.2 Description
The IBM PowerPRS Q-64G Packet Routing
Switch is one of a family of third-generation
switching devices designed for high-performance,
nonblocking, fixed-length packet switching. It
enables the development of scalable switch fabrics
with an aggregate bandwidth of 256 to 512 Gbps.
based on bitmap information contained in the packet
header. To accomplish this, each PowerPRS Q-64G
contains four 16 × 16 subswitch elements con-
nected internally for port expansion. The physical
links between the PowerPRS Q-64G and the
attached devices are high-speed serial links called
Unilinks.
The PowerPRS Q-64G receives packets on up to 32
input ports and routes them to up to 32 output ports
prsq-64g.01.fm
December 20, 2001
General Information
Page 13 of 199
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