IBM3009K2672
IBM SONET/SDH Framer
Receive Transport Overhead Byte Processing
All 81 incoming overhead bytes for each individual STM-1/STS-3c or 324 overhead bytes for STM-4/STM-
4c/STS-12/STS-12c are written into the OFP_Rx# GRA locations. Each of the four SFH block processes the
TOH associated with its corresponding receive STM-1/STS-3c. When STM-4/4c or STM-12/12c streams are
being processed, SFH 1 processes the receive TOH from slot 1 of the frame. B2 errors are accumulated in
SFH 3 since the transmit Z23/M1 byte resides in slot 3 of the transmitted frame. All of the receive
SONET/SDH TOH bytes are passed through the SONET/SDH framer when operating in the Telecom Bus
mode. When processing PPP or ATM data, the TOH is terminated in the SONET/SDH framer. Descrambling
of the line signals can optionally be disabled. The descrambler consists of a frame synchronous descrambler
6
7
with polynomial of 1+X +X . The B1 byte is checked for errors and the errors are counted in a 16-bit counter.
Four separate counters are provided for up to 4 x STM-1/STS-3c operation. Separate B1 block error counters
are also provided.
The SONET/SDH framer also performs a B2 BIP-24 parity check. 16-bit counters with two programmable
thresholds each (for signal fail and signal degradation detection) are provided for counting B2 BIP-24 bit
errors. B2 BIP-24 Block errors are counted in 16-bit performance counters. Two programmable thresholds
are provided for each B2 BIP-24 block error counter. The BIP-24 error counts are optionally provided for
transmission as line FEBE in the Z23/M1 byte. The source is either local, or from the mate SONET/SDH
framer in a ring configuration via the ring port.
The number of consecutive errored framing patterns and the number of bits monitored (all or 12) for OOF can
be configured via the Algo#(1:0) control bits in the PIMRConf2 register. Programmable timer (0, 1, 2, or 3 ms)
is provided for setting the entering or leaving of the LOF state.
Line AIS is automatically inserted downstream within two frames, when a LOF or LOS condition is detected.
A 16-byte long J0 message is stored in the receive GRA. A maskable interrupt request is generated when the
received J0 message does not match a microprocessor-written message. J0 processing can be optionally
disabled or enabled via a control bit.
The K1 and K2 bytes are debounced and placed in the OT#Stat3 and OT#Stat4 registers. If K1 and the first
five MSBs of K2 are equal and new for three (SONET) or five (SDH) consecutive frames, the debounced val-
ues in OT#Stat3 and OT#Stat4 are updated. If the ring port is enabled, the new debounced values along with
a New APS indication are sent to a mate SONET/SDH framer. In addition, bits 6, 7, and 8 of the K2 byte are
monitored for a line RDI (110 ) and a line AIS (111 ) indication. If the ring port is enabled, alarm status can be
2
2
provided, along with interrupt mask bits at the mate SONET/SDH framer. Line RDI status is also provided for
a mate SONET/SDH framer in a ring configuration (Ring Port on page 24) when the ring port is enabled. MS-
AIS is translated into MS-RDI in the transmit direction within two frames. If enabled by the SFen control bit,
excessive error defects can also cause an MS-RDI to be sent in the transmit direction within two frames.
The H1 and H2 bytes for an STM-1 VC-4/STS-3c format and the three H1 and H2 pointer bytes for STS-3 are
processed by pointer tracking state machines to determine the location of the J1 byte in the VC-4 format, or
each of the three J1 bytes in the STS-3 STS-1 formats. The pointer tracking state machine is designed to
meet the current ETSI and Bellcore standards (see Pointer Tracking Interpretation on page 103). In addition,
when operating with the STS-3c/STS-3 formats, the AIS to LOP transition and the ss-bit checks can be dis-
abled to conform to Bellcore/ANSI standards. Upon device reset, the pointer tracking state machines are
forced to the AIS state. Pointer increments, pointer decrements, and New Data Flag (NDF) indications are
counted in their corresponding 8-bit counters. The pointer is also monitored for path AIS and LOP, and inter-
rupt request bits are provided. For STM-4c and STS-12c frames, macros 2-4 monitor the continuous recep-
tion of concatenation indicators and occupy LOP or AIS states (signaled as interrupts) according to the state
machine shown in G.783 annex C.2.
ssframer.01
8/27/99
Operation
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IBM [ IBM ]
