IBM3009K2672
IBM SONET/SDH Framer
The Z23/M1 byte can be monitored for a line FEBE/REI count in a 16-bit performance counter. A control bit is
provided to enable the line FEBE/REI counter to count line FEBE/REI block errors. When operating in 4 x
STM-1/STS-3c mode, any counts greater than 18H are counted as 00H. When STM-4/4c or STS-12/12c
frames are being processed, counts greater than 60H are counted as 00H. For OC-48/STM-16 any count is
accepted.
The received Regenerator Section DCC bytes (D1-D3) or the Multiplex Section Regenerator bytes (D4-D12)
can be output to an external interface. Four of these interfaces are provided, one for each STM-1/STS-3c or
one for each channel of an STM-4/4c or STS-12/12c frame. When a STM-4/4c or STS-12/12c frame is being
processed, only DCC port 1 should be used as there is only one set of DCC bytes in the first channel of those
frames.
The received S1 byte is checked against a microprocessor-written expected value. An interrupt is raised
when a mismatch between the microprocessor-written expected value and the received value persists for a
number of consecutive frames.
No processing is performed on the receive TOH bytes that are reserved for national use or international stan-
dardization.
Transmit Transport Overhead Byte Processing
All 81 outgoing overhead bytes for each individual STM-1/STS-3c or 324 overhead bytes for STM-4/STM-
4c/STS-12/STS-12c are stored in the OFP_Tx# GRA locations by internal logic where they are retrieved for
transmission or for access by a microprocessor. Scrambling of the line signals is provided and can optionally
6
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be disabled. The scrambler consists of a frame synchronous scrambler with polynomial of 1+X +X . When
operating in the Telecom Bus mode, the pointer bytes can be calculated internally (VC-4 mode) or can be
sourced from the TELECOM Bus interface. Additional 16-byte blocks are provided in the transmit GRAs for
transmitting a 16-byte long microprocessor-written J0 message. Optionally C1 byte transmission can be per-
formed for STS slot identification purposes instead of the 16-byte J0 message.
B1 and B2 byte calculations are performed for either four individual STS-3c/STM-1 streams or for a single
STS-12/12c or STM-4/4c stream. B1 and B2 bytes can be corrupted for a single frame by writing to the
desired B1 or B2 location in the transmit GRA.
Four ports are provided for sourcing either the three Regenerator Section DCC bytes (D1-D3) or the Multiplex
Section DCC bytes (D4-D12) associated with the four STM-1/STS-3c streams. The DCC bytes can also be
sourced from the transmit GRA.
When MS-AIS is detected in the receive direction it is translated into MS-RDI in the transmit direction within
two frames. If enabled by the SFen control bit, excessive receive error defects can also cause an MS-RDI to
be sent in the transmit direction within two frames. MS-RDI can also be forced via software control.
MS-AIS can be forced under software control. MS-AIS is all ones in the Multiplex Section bytes and AU-4
bytes.
MS-REI (M1/Z23 byte) generation is based on receive B2 errors. For STM-1/STS-3c operation, receive B2
errors are turned around into MS-REI (in the transmit Z23/M1 byte) on a per SFH basis. For STM-4/4c or
STS-12/12c operation, the receive B2 errors from all four SFHs are accumulated and are then turned around
into MS-REI (in the transmit Z23/M1 byte) in transmit SFH 3. For OC-48/STM-16 applications (where four
SONET/SDH framers are used), the B2 errors from the SFH blocks of each SONET/SDH framer are accumu-
lated and then transferred to SONET/SDH framer 1 where they are summed in SFH 1, and then sent out as
an MS-REI (in the transmit Z23/M1 byte). In OC-48/STM-16 mode, if the summed B2 error count is greater
than FFH, it is truncated at FFH since the transmit M1 byte is only 8 bits long.
Operation
ssframer.01
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