IBM3009K2672
IBM SONET/SDH Framer
C at outputs: 5 pF - 40 pF
L
Symbol
Parameter
Min
30
Typ
Max
60
Unit
ns
%
Notes
tCYC
tPWH / tCYC
tSU1
tH1
GPPCLK clock period
GPPCLK duty cycle
40
GPADDR(13:0) set-up time to GPPCLK↓
GPADDR(13:0) hold time from GPPCLK↓
GPSEL/GPWR/GPRD set-up time to GPPCLK↓
GPSEL/GPWR/GPRD hold time from GPPCLK↓
GPDATA(7:0) input set-up time to GPPCLK↓
GPDATA(7:0) input hold time from GPPCLK↓
GPSEL assertion to GPRDY valid delay
1.0
2.5
6.0
2.0
1.0
2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
tSU2
tH2
tSU3
tH3
tD1
16
16
tD2
GPSEL de-assertion to GPRDY tri-state delay
GPRDY assertion from GPWR/GPRD assertion
GPRDY assertion from GPPCLK↓
4.0
4.5
5.0
2
3
4
tDELAY
tD3
tDELAY(max)
20.5
15
tD4
GPDATA(7:0) output valid delay from GPRDY assertion
GPDATA(7:0) output delay from GPPCLK↓
tD5
18.0
GPDATA(7:0) output valid hold time from GPRD de-
assertion
tH4
tH5
tD6
tr, tf
4.0
3.0
ns
ns
ns
ns
GPDATA(7:0) output valid hold from GPSEL de-assertion
GPDATA(7:0) output tri-state delay from GPRD/GPSEL
de-assertion
17
GPDATA(7:0) output rise and fall times
0.8
8.5
1. This parameter applies to clock transitions during the GPRD/GPWR asserted phase only (when the device is selected); asynchro-
nous signals are acceptable if GPADDR(13:0) change early in the access cycle.
2. There might be a de-asserted (high) phase of GPRDY before turning tri-state if GPRD/GPWR is de-asserted early.
3. To avoid a fast path (GPRDY->READY, WR->GPWR) with the Intel 286 and Intel 386 microprocessors, two internal WAIT states
should be programmed in the device select unit of the microprocessor. Alternatively, the use of a double D-Flip Flop is recom-
mended to delay and re-synchronize the GPRDY falling edge to the microprocessor clock. tDELAY(max) = 5 x tCYC + 6 x tmin, where
tmin is the cycle time of the lowest-frequency chiplet clock. The lowest frequency of the chiplet clocks is the lower of 6.48 MHz or
the UTOPIA interface clock frequencies.
4. The tD3 symbol applies to all read and write cycles with more than one microprocessor WAIT cycle.
Note: The microprocessor interface of the SONET/SDH framer cannot be directly connected to an Intel 286
or Intel 386 microprocessor at 25 MHz or 33.34 MHz clock frequency in synchronous mode because of the
large spread in the timing specifications of these devices. Either device pre-selection for speed, or external
re-synchronizing logic, or a reduction of the microprocessor clock frequency is required for proper operation.
The SONET/SDH framer must be deselected (GPSEL high) between two accesses. It is not recommended to
use the synchronous Intel-type interface due to the requirement for special measures that is indicated Syn-
chronous Microprocessor Interface: Intel-Type Write and Read Cycle Timing on page 86.
ssframer.01
8/27/99
Timing Characteristics
Page 87 of 279
IBM [ IBM ]
