IBM3009K2672
IBM SONET/SDH Framer
UTOPIA Level 2 and Level 2+ Timing
tCYC
TXUCLK1/RXUCLK1
(Inputs)
tPWH
tD
Data/Control
(Outputs)
tSU1
Data/Control
(Inputs)
tH1
C at outputs except for TXCLAV: 5 pF - 40 pF
L
C at TXCLAV outputs: 5 pF - 30 pF
L
Symbol
Parameter
TXUCLK1/RXUCLK1 clock period
Min
19.2
40
Typ
20
Max
Unit
tCYC
ns
%
tPWH / tCYC
TXUCLK1/RXUCLK1 clock duty cycle
TXUCLK1/RXUCLK1 peak-to-peak jitter
TXCLAV delay after TXUCLK1↑
TXABTO delay after TXUCLK1↑
RXUDATA delay after RXUCLK1↑
60
5
%
tD
tD
tD
tD
tD
3.7
3.5
3.3
3.5
3.3
15.7
15
ns
ns
ns
ns
ns
15.5
15
RXCLAV/RXEOFO/RXMSO/RXFCSEO delay after RXUCLK1↑
RXPRTY/RXSOC/RXSOFO/RXABTO delay after RXUCLK1↑
14.5
TXUDATA/TXUADDR/TXPRTY/TXSOC/
TXSOFI/TXENB/TXEOFI/TXMSI set-up time to TXUCLK1↑
tSU1
tH1
tSU1
tH1
3.0
0
ns
ns
TXUDATA/TXUADDR/TXPRTY/TXSOC/
TXSOFI/TXENB/TXEOFI/TXMSI hold time from TXUCLK1↑
RXUADDR/RXENB set-up time to RXUCLK1↑
RXUADDR/RXENB hold time from RXUCLK1↑
UTOPIA interface output rise/fall times
4.0
1.0
0.8
ns
ns
ns
tr, tf
8.0
Note: If the UTOPIA clock frequencies go below 2 MHz, the watchdog timer period (microprocessor interface) may need to be changed.
Timing Characteristics
Page 70 of 279
ssframer.01
8/27/99
IBM [ IBM ]
