IBM3009K2672
IBM SONET/SDH Framer
Boundary Scan Timing
tCYC
tPWL
tPWH
TCK
(Input)
tH1
tSU1
TMS
(Input)
tH2
tSU2
TDI
(Input)
tD
TDO
(Output)
tPW
TRST
(Input)
Note: The timing shown is for the EdgeMode bit of the OR#Conf7 register set to ‘1’.
The timing parameters remain the same when the EdgeMode bit is set to ‘0’, except that
R1DATA# is outputted on the falling edge of the corresponding R1DCLK#.
Each RX Serial DCC interface can be individually configured.
Symbol
tCYC
Parameter1
Min
50
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock period
tPWH / tPWL
tSU1
TCK clock pulse width high/low
TMS set-up time to TCK↑
TMS hold time after TCK↑
TDI set-up time to TCK↑
TDI hold time after TCK↑
TDO delay from TCK↓
TRST pulse width
20
1.0
15
tH1
tSU2
1.0
15
tH2
tD
4.0
50
20
tPW
1. TRST should be stable during the rising transition of FRESET at power on.
Timing Characteristics
Page 74 of 279
ssframer.01
8/27/99
IBM [ IBM ]
