IBM3009K2672
IBM SONET/SDH Framer
UTOPIA Level 1 Timing
tCYC
TXUCLK1/
TXUCLK2
RXUCLK1/
RXUCLK2
(Inputs)
tPWH
tD
Data/Control
(Outputs)
tSU1
Data/Control
(Inputs)
tH1
C at outputs: 5 pF - 40 pF
L
Symbol
Parameter
Min
38.4
40
Typ
40
Max
Unit
tCYC
TXUCLK1/2 / RXUCLK1/2 clock period
TXUCLK1/2 / RXUCLK1/2 clock duty cycle
TXUCLK1/2 / RXUCLK1/2 peak-to-peak jitter
TXCLAV delay after TXUCLK1/2↑
ns
%
tPWH / tCYC
60
5.0
17
%
tD
tD
3.0
3.0
6.0
0
ns
ns
ns
ns
ns
ns
RXUDATA/RXPRTY/RXSOC/RXCLAV delay after RXUCLK1/2↑
TXUDATA/TXPRTY/TXSOC/ TXENB set-up time to TXUCLK1/2↑
TXUDATA/TXPRTY/TXSOC TXENB hold time from TXUCLK1/2↑
RXENB set-up time to RXUCLK1/2↑
17.5
tSU1
tH1
tSU1
tH1
6.0
1.0
RXENB hold time from RXUCLK1/2↑
Note: If the UTOPIA clock frequencies go below 2 MHz, the watchdog timer period (microprocessor interface) may need to be changed.
ssframer.01
8/27/99
Timing Characteristics
Page 69 of 279
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