IBM3009K2672
IBM SONET/SDH Framer
Ring Port Timing
tCYC1
tPWH1
RXRINGCLK
(Output)
tD(min)
tD(max)
RXRINGD
(Output)
tCYC2
TXRINGCLK
(Input)
tPWH2
tSU1
TXRINGD
(Input)
tH1
C at outputs: 3 pF - 25 pF
L
Symbol
Parameter
Min
Typ
Max
Unit
ns
%
tCYC1
tPWH1 / tCYC1
tD
RXRINGCLK clock period
RXRINGCLK clock duty cycle
51.44
43
0
57
5.0
7.0
RXRINGD output delay after RXRINGCLK↓
RXRINGCLK/RXRINGD output rise/fall times
TXRINGCLK clock period
ns
ns
ns
%
tr, tf
1.3
tCYC2
51.44
tPWH2 / tCYC2
tSU1
TXRINGCLK clock duty cycle
35
1.0
2.0
65
TXRINGD set-up time to TXRINGCLK↑
TXRINGD hold time after TXRINGCLK↑
ns
ns
tH1
ssframer.01
8/27/99
Timing Characteristics
Page 67 of 279
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