IBM3009K2672
IBM SONET/SDH Framer
C at outputs: 3 pF - 25 pF
L
Symbol
Parameter
TXCCLK/TXCCLK clock period
Min
Typ
Max
Unit
ns
%
tCYC1
tPWH1 / tCYC1
tD1
51.44
TXCCLK/TXCCLK duty cycle
TXCCLK↑ delay from TXCCLK↓
TXCFRM output delay from TXCCLK↓
TXTB#CLK clock period
42.5
-1.0
-2.5
57.5
1.0
ns
ns
ns
%
tD2
1.0
tCYC2
51.44
tPWH2 / tCYC2
TXTB#CLK duty cycle
35
65
TXTB#DATA(7:0)/TXTB#C1J1/
TXTB#SPE/TXTB#PAR/TXTB#FAIL set-up time to TXTB#CLK↑
tSU1
tH1
tDELAY
tr, tf
1.0
ns
ns
TXTB#DATA(7:0)/TXTB#C1J1/
TXTB#SPE/TXTB#PAR/TXTB#FAIL hold time after TXTB#CLK↑
1.0
Delay from TXCFRM high and TXCCLK↑ to C11 byte clocked in by
TXTB#CLK
3 x tCYC1 - 22
7.0
0
ns
ns
Transmit Telecom Bus interface output rise and fall times
1.3
1. The J1 pulse is not shown in the timing diagram but has the same timing parameters as the C1 pulse. See Functional Relationship
of the Transmit Telecom Bus Signals on page 21.
2. The dashed line shows the TXCFRM pulse when the EFRM control bit is set to ‘1’. The solid pulse shows the TXCFRM pulse when
the EFRM control bit is set to ’0’. Be aware that the tDELAY window always exists with respect to the position that TXCFRM/TXC-
CLK↑ has when the EFRM control bit is ’0’.
3. When transmit retiming is turned off, the C1 pulse in the TXTB#C1J1 signal does not need to be aligned to the C11 byte. In this
case it can be aligned to any byte in the frame.
Timing Characteristics
Page 72 of 279
ssframer.01
8/27/99
IBM [ IBM ]
