IBM3009K2672
IBM SONET/SDH Framer
Receive Serial DCC Interface Timing
tPWL
tPWH
R1DCLK#
(Output)
tCYC
tD1
R1DATA#
(Output)
Note: # = 1-4
C at outputs: 3 pF - 15 pF
L
Symbol
Parameter
R1DCLK# clock period for 192 kbit/s D1-D3 channel
R1DCLK# clock period for 576 kbit/s D4-D12 channel
R1DCLK# clock duty cycle
Min
Typ
5.21
1.73
Max
5.25
Unit
µs
µs
%
tCYC
tCYC
tPWH / tCYC
tD1
5.19
1.7
1.75
45
55
R1DATA# output delay from R1DCLK#↑
51.44 - 3.0
51.44 + 3.0
ns
Note: The timing shown is for the EdgeMode bit of the OT#Conf7 register set to ‘1’. The timing parameters remain the same when the
EdgeMode bit is set to ’0’, except that R1DATA# is output on the falling edge of the corresponding R1DCLK#. Each receive Serial DCC
interface can be individually configured.
Timing Characteristics
Page 64 of 279
ssframer.01
8/27/99
IBM [ IBM ]
