IBM3009K2672
IBM SONET/SDH Framer
Byte-Parallel Transmit Line Interface Timing
tCYC
tPWH
TX_BYCLKINE(1)
TX_BYCLKINE(0)
(Inputs)
TX_BYCLKINT
(Input)
tD1
TXPDAT1(7:0)
(Outputs)
tD2(max)
TXSDOWN#
(Outputs)
tD2(min)
Note: # = 1-4
C at outputs: 3 pF - 15 pF
L
Symbol
tCYC
Parameter
Min
Typ
Max
Unit
ns
%
TX_BYCLKINT/TX_BYCLKINE clock period
TX_BYCLKINT/TX_BYCLKINE clock duty cycle
12.86
tPWH / tCYC
tD1
45
2.3
4.5
0.8
1.3
55
10.1
20
TXPDAT1(7:0) delay after TX_BYCLKINT↑ or TX_BYCLKINE↑
TXSDOWN# delay after TX_BYCLKINT↑ or TX_BYCLKINE↑
TXPDAT1(7:0) output rise/fall times
ns
ns
ns
ns
tD2
tr, tf
4.8
5.8
trC,tfC
TXSDOWN# output rise/fall times
1. TXLPOW# are asynchronous inputs. Asynchronous I/O need not be shown on the timing diagrams.
2. Duty cycles up to 40/60% are acceptable for TX_BYCLKINT/TX_BYCLKINE; but the duty cycle specs of the derived clock outputs
TXCCLK, TXCCLK and RXRINGCLK will also increase by 5%.
ssframer.01
8/27/99
Timing Characteristics
Page 61 of 279
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