IBM3009K2672
IBM SONET/SDH Framer
Serial Transmit Line Interface Timing
tCYC1
REFCLKE(1)
REFCLKE(0)
(Input)
REFCLKT
(Input)
tCYC2
TXDCLKT
(Output)
tCYC3
TXSDAT#(1)
TXSDAT#(0)
(Output)
Note: # = 1-4
C at outputs: 3 pF - 15 pF
L
Symbol
Parameter
Min
Typ
50
Max
Unit
ns
tCYC1
tCYC1
REFCLKT clock period
REFCLKE clock period
12.86
6.43
40
51.44
51.44
60
ns
%
REFCLKT/REFCLKE clock duty cycle
REFCLKT/REFCLKE input rise/fall time
TXDCLKT clock period
1.0
ns
ns
tCYC2
tCYC3
tCYC3
tr,tf
12.86
51.44
TXSDAT1 period
1.61
6.43
ns
ns
ns
ns
TXSDAT2-4 period
TXSDAT1-4 output rise/fall times
TXDCLKT output rise/fall times
0.15
1.3
0.5
5.8
trC,tfC
Notes:
1. Frequencies for REFCLKT and REFCLKE inputs are selected via the Tx_RefFrq(2:0) configuration bits.
2. Frequency for TXDCLKT output is selected via the Tx_DivFrq(2:0) configuration bits.
3. No phase relationship is indicated between REFCLKT/REFCLKE, TXDCLKT, or TXSDAT#.
4. TXLPOW# are asynchronous inputs and TXSDOWN# are asynchronous outputs. Asynchronous I/O need not be shown on the tim-
ing diagrams.
ssframer.01
8/27/99
Timing Characteristics
Page 59 of 279
IBM [ IBM ]
