IBM3009K2672
IBM SONET/SDH Framer
PHY Layer Interface Pin Descriptions (Sheet 1 of 4)
Pin Name
TXUCLK1
Pin No.
A05
I/O
Type
Pin Description
Transmit UTOPIA Clock 1: The data and control signals are transferred
on the rising edge of this clock.
UTOPIA Level 1: This clock is used for transmit UTOPIA Level 1
interface 1. Maximum clock frequency is 25 MHz.
UTOPIA Level 2: This clock is used for the transmit UTOPIA Level 2
interface. Maximum clock frequency is 50 MHz.
I
LVTTL-5sp
UTOPIA Level 2+: This clock is used for the transmit UTOPIA Level
2+ interface. Maximum clock frequency is 50 MHz.
Transmit UTOPIA Clock 2: The data and control signals are transferred
on the rising edge of this clock.
UTOPIA Level 1: This clock is used for transmit UTOPIA Level 1
interface 2. Maximum clock frequency is 25 MHz.
TXUCLK2
C06
I
LVTTL-5sp
UTOPIA Level 2: This clock is not used.
UTOPIA Level 2+: This clock is not used.
TXUDATA(15)
TXUDATA(14)
TXUDATA(13)
TXUDATA(12)
TXUDATA(11)
TXUDATA(10)
TXUDATA(9)
TXUDATA(8)
TXUDATA(7)
TXUDATA(6)
TXUDATA(5)
TXUDATA(4)
TXUDATA(3)
TXUDATA(2)
TXUDATA(1)
TXUDATA(0)
B07
A08
B08
D08
F08
H08
K08
D09
F09
G09
H09
J09
Transmit Data In: 16-bit cell data input, valid when TXENB asserted low.
Bit 0 is the LSB.
UTOPIA Level 1: TXUDATA(15:8) is the data byte input for transmit
UTOPIA Level 1 interface 1. Bit 15 is the MSB and is transmitted first.
TXUDATA(7:0) is the data byte input for transmit UTOPIA Level 1
interface 2. Bit 7 is the MSB and is transmitted first.
UTOPIA Level 2: TXUDATA(15:0) is the word input for the transmit
UTOPIA Level 2 interface. Bit 15 is the most significant bit and is
transmitted first.
UTOPIA Level 2+: TXUDATA(15:0) is the word input for the transmit
UTOPIA Level 2+ interface. Bit 15 is the most significant bit and is
transmitted first.
I
LVTTL-5sp
D10
F10
H10
F11
Transmit Physical Device Address:
UTOPIA Level 1: TXUADDR(4) - TXUADDR(2) are the transmit Par-
ity, Start of Cell, and Enable inputs, respectively, for transmit UTOPIA
Level 1 interface 2.
UTOPIA Level 2: Five-bit wide address for the ports programmed in
this device is provided on TXUADDR(4:0). Bit 0 is the LSB. If single-
PHY operation is performed, such as when STM-4c or STS-12c
frames are processed, then these pins should be set to ’0’.
UTOPIA Level 2+: Five-bit wide address for the ports programmed in
this device is provided on TXUADDR(4:0). Bit 0 is the LSB. If single-
PHY operation is performed, such as when STM-4c or STS-12c
frames are processed, then these pins should be set to ’0’.
TXUADDR(4)
TXUADDR(3)
TXUADDR(2)
TXUADDR(1)
TXUADDR(0)
B09
A10
C10
B11
B12
I
I
LVTTL-5sp
Transmit Parity Input: Odd parity bit for UTOPIA Level 2+, Level 2, and
LVTTL-5sd Level 1 #1 interfaces. Parity can be calculated over data, or data and con-
trol signals, depending on a control bit setting.
TXPRTY
D13
Transmit Start-of-Cell/Chunk Input: Indicates the start of cell/chunk for
LVTTL-5sd
TXSOC
TXSOFI
TXENB
D12
G11
K09
I
I
I
UTOPIA Level 2+, Level 2, and Level1 #1 interfaces.
Transmit Start-of-Frame Input: Used only during UTOPIA Level 2+ oper-
LVTTL-5sd
ation, this pin indicates the start-of-frame data.
Transmit Read Enable Input: Read enable signal for cell input for UTO-
LVTTL-5sp
PIA Level 2+, Level 2, and Level 1 #1 interfaces.
Pin Information
Page 32 of 279
ssframer.01
8/27/99
IBM [ IBM ]
