IBM3009K2672
IBM SONET/SDH Framer
SONET / SDH Pin Descriptions (Sheet 3 of 3)
Pin Name
Pin No.
I/O
Type
Pin Description
SONET/SDH Receive Byte Clock:
RXBYCLK1
A09
I
LVTTL-5sp
Byte clock for the parallel input data on RXPDAT1. Possible clock rate is:
77.76 MHz for STM-4/STM-4c/STS-12/STS-12c.
Receive Divided Clock 1:
RXDCLKT1
RXDCLKT2
RXDCLKT3
RXDCLKT4
E16
C18
O (T)
O (T)
O (T)
O (T)
LVTTL-5s Programmable clock output derived from the serial data stream on channel 1.
Clock rates are 19.44, 38.88, 51.84 and 77.76 MHz.
Receive Divided Clock 2:
LVTTL-5s Programmable clock output derived from the serial data stream on channel 2.
Clock rates are 19.44, 38.88, 51.84 and 77.76 MHz.
Receive Divided Clock 3:
LVTTL-5s Programmable clock output derived from the serial data stream on channel 3.
Clock rates are 19.44, 38.88, 51.84 and 77.76 MHz.
Y17
Receive Divided Clock 4:
LVTTL-5s Programmable clock output derived from the serial data stream on channel 4.
Clock rates are 19.44, 38.88, 51.84 and 77.76 MHz.
AA17
Lock Detect 1:
Signal from external SDH/SONET deserializer indicating that its PLL has
locked to the incoming serial data stream. This pin is used when operating
with the receive parallel line interface.
LOCKDET1
D19
I
LVTTL-5sd
LOSSSIG1
LOSSSIG2
LOSSSIG3
LOSSSIG4
F13
G13
H13
H12
I
I
I
I
LVTTL-5sp Loss of Signal 1: Signal from optical receiver indicating loss of signal.
LVTTL-5sp Loss of Signal 2: Signal from optical receiver indicating loss of signal.
LVTTL-5sp Loss of Signal 3: Signal from optical receiver indicating loss of signal.
LVTTL-5sp Loss of Signal 4: Signal from optical receiver indicating loss of signal.
Out Of Frame 1:
Signal to the external SDH/SONET deserializer/demux indicating that frame
synchronization has been lost and that the deserializer/demux should resume
searching for the frame pattern. This pin is used when operating with the
receive parallel line interface. If an out of frame condition exists then OOF1 is
low. If n consecutive bad framing patterns are received (where n = 4 or 5 con-
figurable), OOF1 goes high. Depending on the deserializer used, either the
high level or this low to high transition will cause the external deserializer to
resynchronize to the framing pattern. The external deserializer will pulse FP1
high for one clock cycle as it resynchronizes. If the next framing pattern after
the pulse on FP1 is correct, the OOF1 will be driven low and remain low. If
this framing pattern is incorrect OOF1 will be driven low for two clock cycles
and then driven high again. Once again, either the edge or the high level will
cause the external deserializer to resynchronize to the framing pattern and
the process repeats. If three consecutive frame-periods elapse since the low
to high transition of OOF1 and no pulse has been received on FP1, OOF1 will
be driven low for two clock cycles then driven high again.
OOF1
D17
O (T)
LVTTL-5sd
Frame Pulse 1:
Signal from an external SDH/SONET deserializer/demux e.g., AMCC 3017.
Pulsed high for one clock cycle to indicate the boundary of an SDH/SONET
frame. For OC-48 applications this signal will normally be aligned to the first
SPE/VC-4 byte of the first row of the SONET/SDH frame. This pin is used
when operating with the receive parallel line interface. The A2Frm control bits
in the OFPRXGP2 register control the required alignment of the FP1 signal.
FP1
A12
H19
I
LVTTL-5sd
LVTTL-5sd
Reset Deserializer 1:
Signal to force a reset of external deserializer. The level used to reset
depends on the deserializer. This pin is used when operating with the receive
parallel line interface.
RSTCREC1
O
ssframer.01
8/27/99
Pin Information
Page 31 of 279
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