IBM3009K2672
IBM SONET/SDH Framer
JTAG / LSSD / Analog Test Interface Pin Descriptions (Sheet 2 of 2)
Name
Pin No.
I/O
Type
Description
JTAG Test Data Output: Output port for serial scan data. It should be left
unconnected if no JTAG test is done.
TDO
P17
O
LVTTL-5s
NCTY(0): LSSD test clock input for SERDES section. This input is con-
nected to an internal pull-up resistor on the chip. It should be left uncon-
nected.
NCTY(0)
NCTY(1)
T19
P19
I
I
I
I
I
NCTY(1): LSSD test clock input for SERDES section. This input is con-
nected to an internal pull-up resistor on the chip. It should be left uncon-
nected.
LSSD_TAP_C1/_C2 Clock: LSSD test clocks for TAP controller. These
inputs are each connected to a pull-up resistor on the chip. They should be
left unconnected.
LSSD_TAP_C1
LSSD_TAP_C2
AC05
AC07
NCTZ(0): LSSD test clock input for SERDES section. This input is con-
nected to an internal pull-up resistor on the chip. It should be left uncon-
nected.
NCTZ(0)
NCTZ(1)
C15
K19
NCTZ(1): LSSD test clock input for SERDES section. This input is con-
nected to an internal pull-up resistor on the chip. It should be left uncon-
nected.
TCSEN: LSSD control signal. This input is connected to a pull-up resistor
in the chip; it should be left unconnected.
TCSEN
PLLTEST
C11
C09
D11
E09
I
PLL Test Enable: Used for module-level PLL tests. This input is con-
nected to a pull-down resistor in the chip. It should be left unconnected.
I
MUXDIVCLK: Diagnostic output of the SERDES section. This output is
connected to an internal pull-down resistor on the chip.
MUXDIVCLK
MUXLOCK
O
O
MUXLOCK: PLL test output, used together with PLLTEST. This output is
connected to an internal pull-down resistor on the chip.
System Pin Descriptions
Pin Name
Pin No.
I/O
I
Type
Pin Description
ATM Cell Handler Clock:
LVTTL-
5sp
This is an asynchronous 25 MHz clock for the ATM cell handler part of the
SONET/SDH framer. This clock can have a frequency lower than 25 MHz
but cannot go below the 19.44 MHz clock used by the transmit SFH blocks.
ACHCLK
N01
SONET/SDH Framer Chip Address:
When there is more than one SONET/SDH framer on a board for OC-
48/STM-16 applications, these pins are used to give each device a unique
LVTTL- address. Bit 0 is the LSB. In OC-48/STM-16 operation the valid range of
ADDR(2)
ADDR(1)
ADDR(0)
U15
V16
U17
I
5sd
ADDR(2:0) would be set to 000-011.
These pins are connected to pull-down resistors in the chip. The default
address is therefore 000. These pins should be left floating or pulled down
for single-device operation (i.e., for non OC-48/ STM-16 applications).
Pin Information
ssframer.01
8/27/99
Page 28 of 279
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