IBM3009K2672
IBM SONET/SDH Framer
SONET / SDH Pin Descriptions (Sheet 1 of 3)
Pin Name
Pin No.
I/O
Type
Pin Description
Serial SONET/SDH Transmit Data 1: (0=true, 1=inverted)
PPECL Bit-serial data to electro/optical transceivers.
Only TXSDAT1 is active in STS-12/12c, STM-4/4c modes.
TXSDAT1(0)
TXSDAT1(1)
H18
G19
O
Serial SONET/SDH Transmit Data 2: (0=true, 1=inverted)
PPECL Bit-serial data to electro/optical transceivers.
Not active in STS-12/12c, STM-4/4c modes.
TXSDAT2(0)
TXSDAT2(1)
L19
M18
O
O
O
Serial SONET/SDH Transmit Data 3: (0=true, 1=inverted)
PPECL Bit-serial data to electro/optical transceivers.
Not active in STS-12/12c, STM-4/4c modes.
TXSDAT3(0)
TXSDAT3(1)
R19
T18
Serial SONET/SDH Transmit Data 4: (0=true, 1=inverted)
PPECL Bit-serial data to electro/optical transceivers.
Not active in STS-12/12c, STM-4/4c modes.
TXSDAT4(0)
TXSDAT4(1)
W19
Y18
TXPDAT1(7)
TXPDAT1(6)
TXPDAT1(5)
TXPDAT1(4)
TXPDAT1(3)
TXPDAT1(2)
TXPDAT1(1)
TXPDAT1(0)
A16
B16
C19
B19
A18
B18
B17
A17
Parallel SONET/SDH Transmit Data:
Byte-parallel data to external SONET/SDH serializer/mux such as
AMCC3018. TXPDAT1(0) is the LSB.
O (T)
LVTTL-5fp
Transmit Reference Clock TTL:
Reference clock inputs for the transmit clock generation system in the
LVTTL-5sd SONET/SDH framer.
REFCLKT
M19
I
I
The frequency of this clock can be selected via control bits to be either 19.44,
38.88, 51.84 or 77.76 MHz.
Transmit Reference Clock ECL: (0=true, 1=inverted)
Reference clock inputs for the transmit clock generation system in the
SONET/SDH framer.
REFCLKE(0)
REFCLKE(1)
D18
C17
LPECL
There is an internal 100Ω resistor connected across these pins.
The frequency of this clock can be selected via control bits to be either 19.44,
38.88, 51.84, 77.76 or 155.52 MHz.
Transmit Divided Clock:
Programmable external clock output with nominal 50% duty cycle.
The level and speed are selectable via control bits.
Frequencies of 19.44, 38.88, 51.84 and 77.76 MHz are available.
TXDCLKT
E17
A15
O (T)
LVTTL-5s
SONET/SDH Transmit Byte Clock TTL:
Byte clock for the parallel transmit interface supplied by the transmit clock
system on the board, or by the external serializer/mux.
TX_BYCLKINT
I
LVTTL-5sp
The clock rate is 77.76 MHz for STM-4/STM-4c/STS-12/STS-12c.
SONET/SDH Transmit Byte Clock ECL: (0=true, 1=inverted)
Byte clock for the parallel transmit interface supplied by the transmit clock
system on the board, or by the external serializer/mux.
The clock rate is 77.76 MHz for STM-4/STM-4c/STS-12/STS-12c.
TX_BYCLKINE(0)
TX_BYCLKINE(1)
F14
E15
I
I
LPECL
There is an internal 100 Ω resistor connected across these pins.
Transmitter Low Power 1:
From external optical transmitter indicating low power output. In parallel
mode, only TXLPOW1 is used.
TXLPOW1
K16
LVTTL-5s
ssframer.01
8/27/99
Pin Information
Page 29 of 279
IBM [ IBM ]
