IBM3009K2672
IBM SONET/SDH Framer
JTAG / LSSD / Analog Test Interface Pin Descriptions (Sheet 1 of 2)
Name
Pin No.
I/O
Type
Description
LSSD Test A clock: Used for factory test of the device. This input is con-
nected to a pull-up resistor in the chip. It should be left unconnected.
LSSD_A
A13
I
LSSD Test B clock: Used for factory test of the device. This input is con-
nected to a pull-up resistor in the chip. It should be left unconnected.
LSSD_B
LSSD_C
A11
A07
C13
V19
I
I
I
I
LSSD Test C clock: Used for factory test of the device. This input is con-
nected to a pull-up resistor in the chip. It should be left unconnected.
LSSD Test ECL clock: Used for factory test of the device. This input is
connected to a pull-up resistor in the chip. It should be left unconnected.
SIM_ECL
TESTGRAC
LSSD Reset GRA-C clock: Used for factory test of the device. This input
is connected to a pull-up resistor in the chip. It should be left unconnected.
Receiver Inhibit:
a) Inhibits all non-test input buffers and forces internal signals connected to
them to known values.
RI
H17
I
b) Disables any pull-up resistors to enable IDDQ testing.
This input must be tied high.
Driver Inhibit, non-test: Inhibits all non-test output buffers. This input is
DI1
DI2
V01
V03
I
I
connected to a pull-up resistor in the chip. It should be left unconnected.
Driver Inhibit, test: Inhibits all test output buffers. This input is connected
to a pull-up resistor in the chip. It should be left unconnected.
Leakage Test: Disables on-chip circuits that draw direct current, enabling
IDDQ measurements to be made. This input is connected to a pull-up
resistor in the chip. It should be left unconnected.
LT
M05
I
Chip Reset: The use of this pin at power-up is mandatory. Holding this
pin low causes all the registers in the device to be reset and, provided that
TRST is low, the following output drivers to be driven high-Z:
TXPDAT1(7:0), TXDCLKT, RXDCLKT1-4, OOF1, all UTOPIA and Tele-
com Bus outputs, microprocessor interface outputs, all APS interface sig-
nals, all Expansion interface outputs, all Ring Port outputs, and the
ALARM4(4:0) outputs.
FRESET
E13
I
LVTTL-5sp
The minimum reset pulse width is 10 microseconds. The power and the
GPPCLK clock input must be stable during the low to high transition of this
pin. The reset pulse applied to this pin should have a rise time less than or
equal to 5 ns.
LSSD Test Enable: This input is connected to an internal pull-down resis-
TEST_MODE
IOTEST
E11
T15
I
I
tor on the chip. It should be left unconnected.
LSSD TAP IO Test: Overrides TAP controller and allows the I/O pins to be
observed and controlled by the tester. For factory device test only. This
input is connected to a pull-down resistor in the chip. It should be left
unconnected.
JTAG TAP Test Clock: Clock input for JTAG boundary scan testing. This
LVTTL-5sp input is connected to a pull-up resistor on the chip. It should be left uncon-
nected if no JTAG test is done.
TCK
TRST
TMS
V17
K17
M17
I
I
I
JTAG TAP Reset: Resets the JTAG TAP controller. If the JTAG is not
LVTTL-5sp
used, an external pull-down resistor can be connected to this pin.
JTAG Test Mode Select: Mode selection for JTAG TAP controller. This
LVTTL-5sp input is connected to a pull-up resistor on the chip. It should be left uncon-
nected if no JTAG test is done.
JTAG Test Data Input: Input port for serial scan data. This input is con-
LVTTL-5sp nected to a pull-up resistor on the chip. It should be left unconnected if no
JTAG test is done.
TDI
T17
I
ssframer.01
8/27/99
Pin Information
Page 27 of 279
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