IBM3009K2672
IBM SONET/SDH Framer
be used by external devices that are supplying data to the transmit Telecom Bus interfaces. Failure input and
outputs are provided for each Telecom Bus interface. In the receive direction, these pins signal to a down-
stream device that conditions for generating Path AIS have been detected by the SONET/SDH framer. In the
transmit direction, these pins signal to the SONET/SDH framer to generate Path AIS in the transmit direction.
There are four individual ATM/PPP Handler blocks. These process the ATM/PPP data and interface to the
Transmit APS Cross Connect (TACC) and Receive APS Cross Connect (RACC) blocks. When processing
ATM Cells or PPP data, each ATM/PPP block provides a four-cell deep FIFO for clock separation in each
direction. Cell rate decoupling is also performed where idle or unassigned cells can be generated. The
header and payload bytes of the idle or unassigned cells in the transmit direction can be programmed via the
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microprocessor interface. A 1+X polynomial payload scrambler/descrambler function can be enabled via a
global control bit for PPP operation. The scrambler/descrambler is always activated when ATM processing is
performed.
When the ATM/PPP Handler blocks are processing PPP data, they perform octet stuffing of flag characters
(7E Hex) and control escape characters (7D Hex) in the transmit direction, and in the receive direction all con-
trol escape characters are destuffed. These blocks can optionally perform 16-bit or 32-bit FCS generation/cal-
culations as selected via global control bits. Frame delimiting and inter-frame flag fill are provided in the
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transmit direction. An optional 1+X polynomial scrambler/descrambler function can be enabled via a global
control bit. Also a transparent mode of operation is possible, for applications where the PPP in “HDLC-like
framing” processing is performed external to the SONET/SDH framer. Registers for programming maximum
and minimum allowable received frame lengths are provided. Received frames that exceed the maximum pro-
grammed frame length are always discarded. Received frames that are below the minimum programmed
frame length may optionally be discarded.
The ATM/PPP Handlers can work individually or in concert with each other depending upon the type of pay-
load being processed. If four individual STM-1/STS-3c frames are being processed, such as in the case of
STM-4/STS-12 or four individual 155 Mb/s streams, then the ATM/PPP blocks work individually. If a STM-
4c/STS-12c is being processed, then all four ATM/PPP blocks work in parallel. The ATM/PPP blocks interface
to the TACC and RACC (transmit and receive APS Cross Connect) blocks.
APS functions are facilitated via an APS interface and the TACC/RACC blocks. These blocks consist of two
5 x 5 cross-connects and two bidirectional APS interfaces, one for transmit and one for receive. The 5 x 5
cross connects handle the data from the four receive/transmit macros plus the receive/transmit APS interface.
If a single SONET/SDH framer is used, 1:1, 1:2, and 1:3 APS is supported. If more than one SONET/SDH
framer is used, such as in a multiple STM-1/STS-3c situation, a 1:N (N = 1 - 14) protection scheme can be
achieved, provided that the two bidirectional APS interfaces are used. The APS function is not available when
the Telecom Bus interface is used, or when concatenated payloads such as AU-4-4c are being processed.
The UTOPIA Level 2+ block interfaces to the four ATM/PPP Handler macros. ATM cells and PPP in “HDLC-
like framing” are handled by this block. For ATM cells, the UTOPIA Level 2+ block can provide either two 8-bit
transmit/receive UTOPIA Level 1 PHY interfaces, or a 16-bit transmit/receive UTOPIA Level 2 PHY interface.
Only cell level handshaking is provided. For UTOPIA Level 2+ MPHY operation, 5-bit address registers allow
addresses to be assigned to the four individual ATM/PPP Handler macros. For PPP operation, the UTOPIA
Level 2+ interface is used with some additional handshaking signals to provide a 16-bit MPHY interface for
passing PPP data in the form of programmable-size chunks. Chunk sizes can be programmed to be either 16,
32, 48, or 64 bytes in length. Indications for aborted frames and FCS errors are also provided. As is the case
for ATM operation, 5-bit address registers allow addresses to be assigned to the four individual ATM/PPP
Handler macros. The UTOPIA Level 1 interfaces can be operated at frequencies up to 25 MHz, while the
UTOPIA Level 2 interface can be operated up to 50 MHz.
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Overview
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