IBM3009K2672
IBM SONET/SDH Framer
• Microprocessor interface.
• Transmit/receive Ring Port (included in SFH block).
• OC-48/STM-16 Expansion Port (included in SFH block).
• Boundary Scan Port.
The SONET/SDH framer can extract ATM/PPP traffic from up to four individual STM-1/STS-3c streams or a
single STM-4/4c or STS-12/12c stream and supply them to its receive UTOPIA Level 2 or Level 2+ interface.
Conversely, the SONET/SDH framer can accept ATM/PPP traffic on its transmit UTOPIA Level 2 or Level 2+
interface and map the ATM/PPP streams into up to four individual STM-1/STS-3c streams or a single STM-
4/4c or STS-12/12c. Other payloads can be handled via the transmit and receive Telecom Bus interfaces.
A high level discussion of the features of the various blocks is given below.
Line Interface and General Data Flow
The Line interface section of the SONET/SDH framer performs the adaptation between the external
SONET/SDH signals and the internal SFH macros.
There are four individual transmit paths that each can handle a single STM-1/STS-3c. Apart from the line
interface, the transmit paths are identical and each is composed of the following macros: UTOPIA or Telecom
Bus interface, APH, TACC, SFH, and LIU. There are four separate Telecom Bus interfaces, each capable of
handling one STM-1/STS-3c stream. Each Telecom Bus has an 8-bit data path with control signals for identi-
fying the VC-4/SPE, and certain overhead bytes.
The macros contained in the four transmit data paths can operate in parallel as one composite macro to sup-
port STM-4/4c or STS-12/12c traffic. The four transmit Telecom Bus interfaces can also operate in parallel as
one composite Telecom Bus with a 32-bit data path.
The transmit line interface of the SONET/SDH framer consists of four LIUs and a byte-parallel interface. All
four LIUs provide clock synthesis for 155.52 Mb/s serial operation with the added feature that LIU #1 can also
perform clock synthesis for 622.08 Mb/s serial operation. A byte-parallel interface is provided in LIU #1 for
622.08 Mb/s operation, but no clock synthesis is provided.
Several options are available. If four individual STM-1/STS-3c streams are desired, the four transmit paths act
independently and four 155.52 Mb/s streams are provided. If an STM-4/STS-12 signal is desired, the four
individual payloads (AU-4/STS-3c SPE) signals are byte-interleaved with TOH (MS and RS) added and
scrambled to form a 622.08 Mb/s serial or byte-parallel stream. However, each of the four transmit paths is
processing an AU-4/STS-3c SPE. When a STM-4c/STS-12c signal is to be transmitted, the peer macros in
the four transmit paths operate together as one large macro. In this case, if the Telecom Bus is used, the four
transmit Telecom Bus interfaces act as one large Telecom Bus with a 32-bit wide datapath.
Clock synthesis, as mentioned above, is provided in the transmit direction for the serial interfaces for sourcing
data at the serial transmit outputs. One reference clock with selectable frequencies of 19.44 MHz, 38.88 MHz,
77.76 MHz, or 155.52 MHz is used to provide the timebase for all four transmit SONET/SDH streams. How-
ever, if the byte-parallel interface is used (for STM-16/OC-48 applications), the external MUX/DEMUX will
have to provide a byte clock to the SONET/SDH framer and perform the clock synthesis function. Scrambling
is still performed.
The process of extracting data in the receive direction is similar to that in the transmit direction, but the flow is
in the opposite direction.
There are four individual receive paths that each can handle a single STM-1/STS-3c. Apart from the line inter-
Block Diagram and Block Descriptions
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ssframer.01
8/27/99
IBM [ IBM ]
