IBM3009K2672
IBM SONET/SDH Framer
face, the receive paths are identical and each is composed of the following macros: UTOPIA or Telecom Bus
interface, APH, RACC, SFH, and LIU. There are four separate Telecom Bus interfaces each capable of han-
dling one STM-1/STS-3c stream. Each Telecom Bus has an 8-bit data path with control signals for identifying
the VC-4/SPE, and certain overhead bytes.
The macros contained in the four receive data paths can operate in parallel as one composite macro to sup-
port STM-4/4c or STS-12/12c traffic. The four receive Telecom Bus interfaces can also operate in parallel as
one composite Telecom Bus with a 32-bit data path.
The receive Line interface of the SONET/SDH framer consists of four LIUs and a byte-parallel interface. All
four LIUs provide clock recovery for 155.52 Mb/s serial operation with the added feature that LIU #1 can also
perform clock recovery for 622.08 Mb/s serial operation. A byte-parallel interface is provided in LIU #1 for
622.08 Mb/s operation, but no clock recovery is provided.
The receive Line interface of the SONET/SDH framer provides several options. If four individual STM-1/STS-
3c streams are to be processed, the four receive paths act independently and four 155.52 Mb/s streams can
be input to the SONET/SDH framer. If an STM-4/STS-12 signal is to be processed, the four individual pay-
loads are byte de-muxed from the applied 622.08 Mb/s serial or byte-parallel stream and are descrambled as
appropriate. However, each of the four receive paths is processing a single payload stream. When a STM-
4c/STS-12c signal is to be processed, the peer macros in the four receive paths operate together as one
large macro. In this case, if the Telecom Bus were being used, the four receive Telecom Bus interfaces would
act as one large Telecom Bus with a 32-bit wide datapath.
As mentioned above, clock recovery is provided in the receive direction for the serial interfaces. However, if
the byte-parallel interface is used, an external OC-48/STM-16 MUX/DEMUX will have to provide a byte clock
to the SONET/SDH framer and perform the clock recovery function. Additionally, byte alignment will need to
be performed by the external OC-48/STM-16 MUX/DEMUX.
SDB - SONET/SDH Data Buffer
The SDB buffers consist of 63-byte deep FIFOs in the transmit direction and 7-byte deep FIFOs in the receive
direction. There is one SDB per SFH macro. The purpose of the SDB is to facilitate the transfer of data
between the APH and the SFH blocks, which operate off of different clock islands.
RACC and TACC - Receive/Transmit APS Cross Connect
The TACC and RACC blocks consist of two separate 5 x 5 cross connects and two separate byte-wide bidi-
rectional APS interfaces. Switching is supported by the RACC while bridging and switching are supported by
the TACC. Command of the switching and bridging is accomplished through two microprocessor-accessible
control registers. Upon power-up, each APH macro is bridged to its corresponding SFH. When a switch is
performed, the output of the SFH (which is typically a C-4 signal) is switched. In single device operation, there
can be three working channels and one protection channel. If a failure occurs on one of the working channels,
the TACC is configured to bridge the output of the APH macro for the failing line over to the protection chan-
nel’s SFH. The RACC is configured to switch the output of the SFH of the protection channel over to the APH
of the working channel. This operation is shown in the two figures on page 10.
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Block Diagram and Block Descriptions
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