IBM3009K2672
IBM SONET/SDH Framer
Two loopbacks are supported in the transmit direction and one is supported in the receive direction for
ATM/PPP payloads. All of the loopbacks occur at the TCS (Transmission Convergence Sublayer) Function
Boundaries of the ATM/PPP Handler. The first transmit loopback is at the ATM Cell Buffer (ACB) interface with
the ATM/PPP Handler. As soon as the ACB is not empty, the ACB contents are read and provided to the
receive direction. The second transmit loopback is at the output of the ATM/PPP Handler before the SFH. The
transmit cell stream at the output of the ATM/PPP Handler is looped back to the receive side of the ATM/PPP
Handler. This cell stream can contain idle/unassigned cells. Each of the transmit loopbacks has two modes.
With the first mode, just the loopback is performed and data is not forwarded to the next processing step in
addition to being looped back. The second loopback mode allows data to be forwarded to the next processing
step. The receive loopback causes receive data provided by the SFH to be looped back towards the transmit
direction. There are two modes for the receive loopbacks: one for loopback only (i.e., no data is passed to the
ATM/PPP Handlers), and one where data is also passed to the ATM/PPP Handler.
The SONET/SDH framer provides a microprocessor interface that can be selected to be compatible with the
Motorola 68360 processor bus type interface (QUICC bus type), or the Intel style bus. The interface can be
selected to be either synchronous or asynchronous. The synchronous interface can be run with a maximum
clock frequency of 33.3 MHz, while the asynchronous interface can be run with a 50 MHz clock. Polling or
interrupt support, and latching of critical events, are provided to accelerate interrupt processing and reduce
the burden on the microprocessor. Alarm masks are provided to enable or disable interrupts. Overflow and
programmable threshold interrupts are provided on certain counters. An integrated watchdog timer is pro-
vided with a programmable period to force microprocessor accesses to terminate when a timeout occurs.
Access to the various configuration registers, counters, and the control and status registers is provided via
this microprocessor interface.
There are many features included in the SONET/SDH framer that make it well suited for higher-order multi-
plex applications. The integrated APS Cross Connect Circuit reduces external part counts. In STS-48/
STM-16 applications, the SONET/SDH framer can support multiplexing of STM-4, STM-4c, STS-12, or
STS-12c frames. Telecom Bus, Dual UTOPIA Level 1 and UTOPIA Level 2 interfaces add a high degree of
flexibility for connecting to ATM or PPP terminating/switching equipment or other path terminating equipment.
On-chip clock recovery and synthesis for the serial 155 Mb/s or 622 Mb/s interfaces eliminates the need for
additional external clock recovery circuitry. The high degree of integration of complex functional blocks into a
single device with glueless device-to-device communication for multi-device applications makes possible
reduced design and debug time and shorter time to market.
The Boundary Scan Port includes a five-pin TAP (Test Access Port) that conforms to the IEEE 1149.1-1994
standard. This TAP provides external boundary scan to read and write the SONET/SDH framer input and out-
put pins from the TAP for circuit board and component testing.
Overview
ssframer.01
8/27/99
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