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IBM3009K2672
IBM SONET/SDH Framer
Features
• Integrated clock recovery and synthesis for four
OC-3c/STM-1 signals or one OC-12/OC-12c/
STM-4/STM-4c signal
• Quad byte-parallel Telecom Bus at 19.44 MHz
• Access to Line or Section DCC via a port
• Ring port for USHR/P support
• OC-12/STM-4 or quad OC-3c/STM-1 framing
and performance monitoring
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• Selectable Intel /Motorola-compatible micropro-
cessor interface
• Expansion port for OC-48/STM-16 operation
• Boundary scan capability (IEEE 1149.1)
• 0.35 micron CMOS technology
• Single +3.3 V, 5% power supply
• Complete Transport/Section Overhead process-
ing and generation conforming to Bellcore and
ITU-T standards
• 5 V tolerant input/output interfaces (except to
line)
• Complete Path Overhead processing and gen-
eration for one STS-12c/STM-4c signal or for
four STS-3c/STM-1 signals for ATM/PPP
• Approx. 4.1 W typ. (four 155 Mb/s interfaces),
approx. 3.3 W typ. (one interface at 622 Mb/s)
• VC-4 cross-connect, APS for ATM/PPP pay-
loads using the UTOPIA port(s)
• 474-pin ceramic ball grid array package initially
• Plastic ball grid array package in future
• Cell or frame delineation function for four
155 Mb/s signals or one (concatenated or
unconcatenated) 622 Mb/s signal
• SONET/SDH add/drop or higher-order terminal
multiplexers
• “PPP” octet stuffing and mapping per RFC1662
and RFC1619 for four 155 Mb/s signals or one
unconcatenated multi-PHY 622 Mb/s signal or
one concatenated single-PHY 622 Mb/s signal
• Transport of ATM/PPP or VT/TU payloads over
SONET/SDH
• Transmission of E1/DS1, E3/DS3 or E4 over
SONET/SDH
• One UTOPIA L2+ (cell/frame) 16-bit interface at
50 MHz or two UTOPIA L1 8-bit at 25 MHz
• ATM switches
Description
IBM3009K2672 is a highly integrated SONET/SDH
terminator device designed for ATM cell, frame,
higher-order multiplexing, and transmission applica-
tions. The primary applications of the SONET/SDH
framer are transport of ATM/PPP payloads over
SONET/SDH, higher-order muxes, and add/drop
muxes. A single IBM SONET/SDH framer can termi-
nate four individual STS-3c or STM-1 lines or a sin-
gle OC-12/12c or STM-4/4c line. Each SONET/SDH
terminator has an associated line interface block
that performs clock synthesis and clock recovery for
four 155.52 Mb/s signals or single 622.08 Mb/s
serial operation. A parallel line interface port and an
expansion port allow four SONET/SDH framers to
operate in unison for OC-48/STM-16 applications.
The SONET/SDH framer can terminate ATM pay-
loads from any of the above signals into either a sin-
gle 16-bit or 8-bit UTOPIA Level 2 PHY interface, or
two 8-bit UTOPIA Level 1 PHY interfaces. PPP pay-
loads are terminated into a 16-bit wide UTOPIA
Level 2+ interface. STM (VT/TU) payloads can be
terminated into four 8-bit wide Telecom Bus inter-
faces. When terminating concatenated payloads,
the four Telecom Bus interfaces act in concert as a
single 32-bit wide Telecom Bus interface. Single-
device APS switching or 1:N APS between multiple
SONET/SDH framers is also provided for ATM and
PPP payloads.
ssframer.01
8/27/99
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