Data Sheet
Preliminary
PowerPC 970FX
Figure 3-4. Typical Implementation for a Single-ended Line
OV
DD
OV
DD
Z
d
TR0
Z0
R
TR0
Z
d
LSSB
V
REF-SSB
Table 3-11. Processor Interconnect SSB Driver Specifications
Symbol
Description
Minimum
Typical
Maximum
Units
Notes
V
DC High output level at DC
DC Low output level at DC
0.87 OV
0.13 OV
133
mV
mV
ps
OH
DD
DD
V
OL
T
Driver rise time
70
81
15
30
171
162
25
20% to 80% of swing
20% to 80% of swing
DR
T
Driver fall time
155
ps
DF
Z
Driver output impedance
Driver output impedance
20
Ohms Low Ohm mode
Ohms High Ohm mode
D
D
Z
40
50
3.5.1.3 Module-to-Module Interconnect Characteristics
All traces are to be routed as striplines or microstrip. The tolerance on trace impedance is 10%. Care must be
taken when mixing transmission line styles to manage propagation delay differences. The clock delay should
be longer than the longest data delay for bus speeds at or above 1.1 Gb/s or on lines above 13 cm.
Table 3-12. Processor Interconnect SSB PCB Trace Specifications
Symbol
Description
Trace length
Minimum
Typical
Maximum
18
Units
cm
Notes
For transfer speeds of 1.5G/s.
For transfer speeds of 1.0G/s.
L
SSB
22.5
55
cm
Z
Trace impedance
45
50
Ohms
ps
0
S
PCB data trace skew
150
DPCB
Electrical and Thermal Characteristics
Page 27 of 74
October 14, 2005
IBM [ IBM ]
