Data Sheet
PowerPC 970FX
Preliminary
3.5.1.4 Receive Side Characteristics
The receive side contains far-end termination circuitry as shown in Figure 3-4 for the single-end lines. The
total skew from the drive side to the module input pins on the receive side is 350ps (SDS+ SPCB) between any
two signals (clocks or data). The differential clock termination scheme is shown in Figure 3-5. All receivers
are pseudo-differential with reference to VREF-SSB and with common-mode rejection of at least 0.5 × VDD
.
VREF-SSB may be generated internally by the receive-side circuitry or may be derived from the supply voltage.
Table 3-13. Processor Interconnect SSB Receiver Specifications
Symbol
Description
Minimum
Typical
Maximum
Units
mV
%
Notes
(V DC + V DC)/2
V
SSB reference voltage
Bus clock duty cycle
Single-ended terminator
0.5 x OV
50
REF-SSB
DD
OH
OL
Bclk
48
83
52
DC
TR0
110
137
Ohms 110 +/-25%
Figure 3-5. Differential Clock Termination Circuitry
OV
OV
DD
DD
R
R
R
C
C
C
Bclk
Bclk
R
C
For high-performance operation, the PI supports the inclusion and operation of receive-side circuitry for clock
alignment and individual bit-level deskew. An initialization alignment procedure (IAP) is activated at power-on
reset (POR) for bit-level deskew and clock alignment. The IAP uses delay elements in the receive-side
circuitry to first equalize the delay of the incoming data signals and then center the clock transition in the
timing window. The timing parameters for the delay elements and flip-flops that register the data signals are
summarized in Table 3-14.
Table 3-14. Processor Interconnect SSB Timing Parameters for the Deskew and Clock Alignment
Symbol
Description
Bit time
Minimum
Typical
Maximum
Units
ns
Notes
T
1/(2xBclk)
BIT
Delay element time
increment
T
T
18
18
25
25
35
35
ps
ps
Thirty-one delay elements for data
Sixty-four delay elements for clock
DED
DEC
Delay element time
increment
Electrical and Thermal Characteristics
Page 28 of 74
October 14, 2005
IBM [ IBM ]
