-- 32-bit address bu s
-- 64-bit data bu s
-- Bu s-to-core frequ en cy m u ltipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x,
7x,7.5x, an d 8x su pported
•· In tegrated power m an agem en t
-- Low-power 2.6/ 3.3-volt design
-- Th ree static power savin g m odes: doze, n ap, an d sleep
-- Au tom atic dyn am ic power redu ction wh en in tern al fu n ction al u n its are idle
•· In tegrated Th erm al Man agem en t Assist Un it
-- On -ch ip th erm al sen sor an d con trol logic
-- Th erm al Man agem en t In terru pt for software regu lation of ju n ction
tem peratu re
•· Testability
-- LSSD scan design
-- J TAG in terface
•· Reliability an d serviceability--Parity ch eckin g on 60x an d L2 cach e bu ses
3.0 General Parameters
Th e followin g list provides a su m m ary of th e gen eral param eters of th e PPC740 an d
PPC750:
Tech n ology
0.25 µm CMOS, five-layer m etal
2
Die Size
7.56 m m x 8.79 m m (67 m m )
Tran sistor cou n t
Logic design
Packages
6.35 m illion
Fu lly-static
PPC740: Su rface m ou n t 255-lead ceram ic ball grid array
(CBGA) with ou t L2 in terface.
PPC750: Su rface m ou n t 360-lead ceram ic ball grid array
(CBGA) with L2 in terface.
Core power su pply
I/ O power su pply
2.6 ± 100m V dc
3.3 V ± 5% V dc
3.1 Electrical and Thermal Characteristics
Th is section provides both AC an d DC electrical specification s an d th erm al ch aracteris-
tics for th e PPC740 an d PPC750.
PPC740 and PPC750 Hardware Specifications
5 of 43
Preliminary and subject to change without notice
IBM [ IBM ]
