arith m etic
-- 3 cycle laten cy, 1 cycle th rou gh pu t, sin gle-precision m u ltiply-add
-- 3 cycle laten cy, 1 cycle th rou gh pu t, dou ble-precision add
-- 4 cycle laten cy, 2 cycle th rou gh pu t, dou ble-precision m u ltiply-add
-- Hardware su pport for divide
-- Hardware su pport for den orm alized n u m bers
-- Tim e determ in istic n on -IEEE m ode
•· System u n it
-- Execu tes CR logical in stru ction s an d m iscellan eou s system in stru ction s
-- Special register tran sfer in stru ction s
•· Cach e stru ctu re
-- 32K, 32-byte lin e, 8-way set associative in stru ction cach e
-- 32K, 32-byte lin e, 8-way set associative data cach e
-- Sin gle-cycle cach e access
-- Pseu do-LRU replacem en t
-- Copy-back or write-th rou gh data cach e (on a page per page basis)
-- Su pports all PowerPC m em ory coh eren cy m odes
-- Non -blockin g in stru ction an d data cach e (on e ou tstan din g m iss u n der h its)
-- No sn oopin g of in stru ction cach e
•· Mem ory m an agem en t u n it
-- 128 en try, 2-way set associative in stru ction TLB
-- 128 en try, 2-way set associative data TLB
-- Hardware reload for TLB's
-- 4 in stru ction BAT's an d 4 data BATs
52
-- Virtu al m em ory su pport for u p to 4 exabytes (2 ) virtu al m em ory
32
-- Real m em ory su pport for u p to 4 gigabytes (2 ) of ph ysical m em ory
•· Level 2 (L2) cach e in terface (n ot in clu ded on th e PPC740)
-- In tern al L2 cach e con troller an d 4K-en try tags; extern al data SRAMs
-- 256K, 512K, an d 1 Mbyte 2-way set associative L2 cach e su pport
-- Copy-back or write-th rou gh data cach e (on a page basis, or for all L2)
-- 64-byte(256K/ 512K) an d 128-byte (l-Mbyte) sectored lin e size
-- Su pports flow-th rou gh (reg-bu f) syn ch ron ou s bu rst SRAMs, pipelin ed
(reg-reg) syn ch ron ou s bu rst SRAMs, an d pipelin ed (reg-reg) late-write
syn ch ron ou s bu rst SRAMs
-- Design su pports Core-to-L2 frequ en cy divisors of ÷1, ÷1.5, ÷2, ÷2.5, an d ÷3.
However, th is specification su pports th e L2 frequ en cy ran ge specified in
Section 3.1.2.4, “L2 Clock AC Specification s“. For h igh er L2 frequ en cies n ot su p-
ported in th is docu m en t, please con tact you r IBM m arketin g represen tative.
•· Bu s in terface
-- Com patible with 60x processor in terface
4 of 43
PPC740 and PPC750 Hardware Specifications
Preliminary and subject to change without notice
IBM [ IBM ]
