1.0 Overview
The PPC740 and PPC750 are targeted for high performance, low power systems and
support the following power management features - doze, nap, sleep, and dynamic
power management. The PPC750 consists of a processor core and an internal L2 Tag
combined with a dedicated L2 cache interface and a 60x bus. The PPC740 is the same
design as the PPC750, except that the L2 interface pins are not brought out on the
package. The PPC740 is meant to be run in applications that do not require an L2.
50.
Control Unit
32K ICache
Dispatch
BHT /
BTIC
Completion
System
Unit
Instruction Fetch
Branch Unit
FXU1
FXU2
Rename
Buffers
GPRs
LSU
FPRs
Rename
Buffers
FPU
32K DCache
L2 Tags
L2 Cache
BIU
60X
BIU
(Not available
in PPC740)
Figure 1. PPC740 and PPC750 Block Diagram
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PPC740 and PPC750 Hardware Specifications
Preliminary and subject to change without notice
IBM [ IBM ]
