1.0 Overview
Th e PPC740 an d PPC750 are targeted for h igh perform an ce, low power system s an d
su pport th e followin g power m an agem en t featu res - doze, n ap, sleep, an d dyn am ic
power m an agem en t. Th e PPC750 con sists of a processor core an d an in tern al L2 Tag
com bin ed with a dedicated L2 cach e in terface an d a 60x bu s. Th e PPC740 is th e sam e
design as th e PPC750, except th at th e L2 in terface pin s are n ot brou gh t ou t on th e
package. Th e PPC740 is m ean t to be ru n in application s th at do n ot requ ire an L2.
Figure 1 shows a block diagram of the PPC740 and PPC750.
Control Unit
Instruction Fetch
Branch Unit
Completion
32K ICache
BHT /
BTIC
System
Unit
Dispatch
GPRs
FPRs
FXU2
LSU
FPU
FXU1
Rename
Buffers
Rename
Buffers
32K DCache
L2 Cache
BIU
60X
BIU
L2 Tags
(Not available
in PPC740)
Figure 1. PPC740 and PPC750 Block Diagram
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PPC740 and PPC750 Hardware Specifications
Preliminary and subject to change without notice
IBM [ IBM ]
