Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signals Listed by Ball Assignment (Part 5 of 7)
Ball
Signal Name
Ball
Signal Name
Ball
W01
W02
W03
W04
W05
W06
W07
Signal Name
Ball
Y01
Signal Name
G_ADH07
V
U01
GND
V01
G_ADH11
DD
U02
U03
U04
U05
U06
U07
G_ADH12
V02
V03
V04
V05
V06
V07
G_ADH10
G_ADH09
G_GNT6
G_GNT5
G_REQ1
G_REQ2
G_ADH08
GND
Y02
Y03
Y04
Y05
Y06
Y07
G_ADH06
G_GNT3
G_GNT2
G_GNT1
G_REQ4
G_REQ5
SYS_DATA00
G_REQ6
V
DD
G_GNT7
GND
G_GNT4
OV
DD
G_REQ0
G_REQ3
GND
OV
DD
V
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
G_CBE2
G_CBE1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SYS_BR1
SYS_BR3
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
PCG_CLK
Reserved
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
DD
G_CBE0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SYS_BR0
V
SYS_AACK
SYS_ARTRY
SYS_MCP2
Reserved
DD
SYS_GBL
GND
SYS_MCP3
OV
SYS_MCP0
Reserved
DD
SYS_MCP1
GND
SYS_TT4
SYS_TT2
SYS_TT1
Reserved
SYS_TT3
V
DD
TCK
V
SYS_DBG1
SYS_BG1
SYS_ADDRP0
SYS_ADDR01
SYS_ADDR02
SYS_ADDR03
SYS_BG2
SYS_TS
DD
OV
U21
U22
U23
U24
U25
U26
U27
V21
V22
V23
V24
V25
V26
V27
SYS_ADDRP3
SYS_ADDRP2
P_SERR
W21
W22
W23
W24
W25
W26
W27
GND
Y21
Y22
Y23
Y24
Y25
Y26
Y27
DD
Reserved
GND
SYS_ADDRP1
OV
DD
P_STOP
P_REQ3
SYS_ADDR00
GND
V
P_REQ2
DD
P_PERR
GND
P_REQ1
P_GNT2
V
P_REQ0
P_GNT1
DD
32
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