Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
Signals Listed by Ball Assignment (Part 4 of 7)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
G_ADH19
Ball
T01
Signal Name
G_ADH16
OV
N01
G_ADH27
P01
R01
DD
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
G_ADH26
GND
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
G_ADH21
G_ADH20
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
G_ADH18
GND
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
T13
G_ADH15
G_ADH14
G_ADH13
G_INTD
G_INTC
G_INTB
GND
V
G_ADH25
G_ADH24
G_ADH23
G_ADH22
G_STOP
Reserved
Reserved
Reserved
Reserved
GND
G_ADH17
G_CBE4
G_ACK64
G_CBE3
G_PAR
DD
G_CBE7
GND
G_CBE6
OV
DD
G_CBE5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
G_INTA
Reserved
Reserved
Reserved
Reserved
V
DD
V
V
N14
P14
GND
R14
T14
Reserved
DD
DD
V
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
GND
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
GND
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
Reserved
Reserved
Reserved
Reserved
SYS_BR2
GND
DD
Reserved
Reserved
Reserved
Reserved
P_ADL26
P_ADL24
P_ADL15
CE0_TEST
P_ADL08
GND
Reserved
Reserved
Reserved
P_ADL31
Reserved
Reserved
Reserved
Reserved
SYS_DBG3
SYS_DBG2
P_DEVSEL
PLL_TUNE4
P_CBE0
GND
OV
DD
P_ADL25
GND
SYS_DBG0
P_FRAME
PLL_TUNE2
P_CBE1
PLL_LOCK
V
DD
P_ADL07
P_ADL00
P_CBE2
P_ADL01
P_RST
TMS
P_CBE3
OV
PLL_TUNE3
P_GNT3
DD
31
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